Arteris Articles

Semiconductor Engineering: Power Optimization: What's Next?

Guillaume Boillet, Director of Product Management at Arteris IP is quoted in this new article in Semiconductor Engineering:

Power Optimization: What's Next!

May 17th, 2021 - By Brian Bailey

Clock gating and power gating were a good start, but there is much more that can and should be done to minimize power.

“The efforts in terms of methodology, compute resources and engineering talent to deploy system-level techniques are definitely non-negligible,” says Guillaume Boillet, director of product management for Arteris IP. “Only the most advanced and power-savvy design teams invest in those.”

Topics: SoC NoC network-on-chip dynamic power machine learning semiconductor engineering arteris ip interconnects RTL Guillaume Boillet clock-gating macro-level

Our Consumer Electronics Really Suck (Power)

For all the work our industry does to implement sophisticated power management and conservation features in our chips and software, I was dismayed (and a little appalled) to read Saturday’s New York Times article, “Atop TV Sets, a Power Drain That Runs Nonstop.”

Topics: power power dissipation idle power dynamic power consumer electronics