Arteris Articles

EE Times article, AI Startups Plateau, AI SoCs Soar, and the Edge Diverges

Laurent Moll, Chief Operating Officer at Arteris IP, sits down with Junko Yoshida in this new EE Times article.

May 13th, 2021 - by Junko Yoshida

Laurent Moll, chief operating officer at Arteris, predicts that in the future, “everyone has some kind of AI in their SoCs.” That is good news for Arteris, because its business is in helping companies (large and small, or new and old) integrate SoCs by providing network-on-chip (NoC) IP and IP development tools.

Topics: semiconductor ADAS eetimes AI SoCs AI chips data centers noc interconnect smartphones SoC IP hyperscalers googles TPU car OEMS edge ai

EE Times article, "Licensing Interconnect IP for Fun & Profit"

Kurt Shuler, VP Marketing at Arteris IP, authored this EE Times article discussing NoC interconnect Build or Buy.

February 25, 2021 - by Kurt Shuler

Why do we buy instead of build? Because the guys at the factory know what they’re doing.

The big question then becomes, which parts do we design in-house, and which do we bring in from outside? That’s a whiteboard architectural discussion, which can be heated and emotional. Engineers want to build stuff — that’s what they do. Managers want to get a working product out the door as economically as possible — that’s what they do. If the engineers want to make, and the managers want to buy, who wins? Who gets to make that call, and how do they justify the decision? 

Topics: SoC economics semiconductor eetimes AI SoCs RTL kurt shuler noc interconnect ML/AI SoC IP R&D costs buy vs build build vs buy

EE Times article, The Age of the Monster Chip

K. Charles Janac, President and CEO, at Arteris IP, authored this article on what is now defined as a "Monster Chip".

September 19, 2019 - by K. Charles Janac

What are the system designs that require a leap in SoC complexity? It’s not only big datacenter artificial intelligence (AI) chips, but also autonomous vehicles such as cars, trucks and drones; they are self-landing, reusable rockets; they are medical devices carrying out remote diagnostics; and they are connected machine tool controllers supporting smart manufacturing.

These chips are starting to be referred to as “Monster Chips” because of both the size and complexity.

Topics: semiconductor ADAS eetimes autonomous driving AI K. Charles Janac SoCs noc interconnect data center automation blockchain big chips

EE Times article, The Gatekeeper of a Successful Design is the Interconnect

K. Charles Janac, President and CEO, at Arteris IP, authored this article on how an effective interconnect makes delivering a complex SoC easier, more predictable, and less costly.

August 25, 2019 - by K. Charles Janac

An interconnect handles various types of traffic inside an SoC and is a mechanism for effective IP block integration. The interconnect is the most configurable IP in the SoC — typically changing many times during a project and nearly always changing between projects. It also plays a vital role in security and functional safety because it carries most of the SoC data and contains nearly all the SoC’s long wires and system-level services, including quality of service (QoS), visibility, physical awareness, and power management. The interconnect enables cache coherency in multiprocessor SoCs, high-performance and bandwidth levels in advanced driver assistance systems (ADAS) automotive chips and networking SoCs, and ultra-low power in long-running consumer devices.

Topics: semiconductor eetimes advanced driver assistance systems adas autonomous driving AI K. Charles Janac SoCs noc interconnect ML data center automation