Arteris Articles

Semiconductor Engineering: Is Hardware-Assisted Verification Avoidable?

Khaled Labib, Vice President of Engineering at Arteris IP is quoted in this new article in Semiconductor Engineering:

Is Hardware-Assisted Verification Avoidable?

October 28th, 2020 - By Brian Bailey

Simulation is no longer up to the task of system-level verification, but making the switch to hardware-assisted verification can lead to some surprises if you do not fully plan ahead.

Bringing hardware-assisted verification in for the first time is not easy. “For a small company, emulation systems are expensive,” says Arteris’ Labib. “The ones with more advanced features run you about a million dollars for an average starting configuration. If you want to start lower than that, you’re going to have to either give up on features or go with a smaller commercial configuration. But this has become critical to our business, and even as a small company we had to find the necessary budget to buy emulation.”

Topics: SoC NoC semiconductor engineering interconnects emulation noc interconnect IP market cloud khaled labib testbench configurable IP solution regression

Semiconductor Engineering: Spiking Neural Networks: Research Projects or Commercial Products?

Michael Frank, fellow and chief architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Spiking Neural Networks: Research Projects or Commercial Products?

May 18th, 2020 - By Byron Moyer

Opinions differ widely, but in this space that isn't unusual.
 
SNN neurons typically are implemented in one of two ways. The approaches are motivated by analog implementations, although they can be abstracted into digital equivalents.  Arteris IP   fellow and chief architect Michael Frank refers to this as “emulation.” He points to several challenges for an analog implementation: “With analog, you would need to customize the model to the specific chip for inference. No two transistors are the same. And at 7 nm, you can’t do analog.”
 
Topics: analog SoC automotive neural networks NoC technology semiconductor engineering emulation noc interconnect IP market SNN multi-cast spike data

Semiconductor Engineering: When Bugs Escape

Chirag Gandi, Director of Verification at Arteris IP, chats with Brian Bailey in this Semiconductor Engineering article:

When Bugs Escape

 

July 26th, 2018 - By Brian Bailey

Topics: SoC semiconductor semiconductor engineering arteris ip interconnects deadlocks emulation silicon RTL formal verification layered verification corner-case bugs