Arteris Articles

Arteris IP Presents: Lessons Learned integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip

This presentation titled, "Lessons Learned integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip," presented by Kurt Shuler, VP of Marketing and Functional Safety Manager (FSM) at Arteris IP, and Diego Botero, Functional Safety Engineer at Arteris IP, to an audience at the ISO 26262 for Semiconductors (Munich) Conference.

Topics: functional safety ISO 26262 Systems-on-Chip FlexNoC kurt shuler accelerators ML/AI automotive chips IQPC

Semiconductor Engineering: 3 Safety Standards In Auto Electronics [Video]

 

Tech Talk Video:
3 Safety Standards in Auto Electronics

January 12th,  2020 - By Ed Sperling

Ed Sperling talks with Kurt Shuler, vice president of marketing at Arteris IP headquarters, about ISO 26262, SOTIF (Safety of the Intended Functionality) and UL 4600, what each one covers, what the intent is behind them, and what this means for companies developing technology for the future vehicles.

Topics: ISO 26262 automotive functional safety FlexNoC safety tech talk video ISO PAS 21448 UL 4600

Arteris IP at Synopsys Users Group Silicon Valley 2019


Arteris IP at SNUG Silicon Valley 2019 

Location: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA  
Track: Artificial Intelligence - Wednesday, 20 March, 3:45 pm - 4:30 pm

Arteris IP is presenting this paper, "Using Machine Learning for Characterization of NoC Components"

Topics: NoC semiconductor FlexNoC Soft IP SoCs RTL noc interconnect ML PPA

SemiWiki: On-Chip Networks at the Bleeding Edge of ML

On-chip networks become a lot more challenging at the high-end of machine learning (ML). Bernard Murphy (SemiWiki) talked with Kurt Shuler, VP Marketing at Arteris IP, about the experience they have developed over the years of working with well-known ML product builders and how this has influenced  the AI package recently released by Arteris IP in this SemiWiki blog:

On-Chip Networks at the Bleeding Edge of ML 

November 29th,  2018 - By Bernard Murphy

I wrote a while back about some of the more exotic architectures for machine learning (ML), especially for neural net (NN) training in the data center but also in some edge applications. In less hairy applications, we’re used to seeing CPU-based NNs at the low end, GPUs most commonly (and most widely known) in data centers as the workhorse for training, and for the early incarnations of some mobile apps (mobile AR/MR for example), FPGAs in applications where architecture/performance becomes more important but power isn’t super-constrained, DSPs in applications pushing performance per watt harder and custom designs such as the Google TPU pushing even harder.

Topics: SoC NoC FPGAs semiconductor machine learning FlexNoC semiwiki kurt shuler AI chips flexnoc ai package