Arteris Articles

Semiconductor Engineering: AI Chips: NoC Interconnect IP Solves Three Design Challenges

 Arteris IP's Kurt Shuler warns that regular topologies, large chips, and huge bandwidths are considerations in AI-centric chips in the date center.

AI Chips: NoC Interconnect IP Solves Three Design Challenges  

January 10th,  2019 - By Kurt Shuler

New network-on-chip (NoC) interconnect IP is now available for artificial intelligence (AI) systems-on-chip (SoC). Arteris IP launched the fourth generation of FlexNoC interconnect IP with a new AI package.

The new NoC technology benefits emerging AI chip architectures in three main ways: automatically generating regular topologies, effectively managing the data flows of large chips with long wires and enabling large on- and off-chip bandwidths.

To learn more, please visit the FlexNoC AI Package page; https://www.arteris.com/flexnoc-ai-package and the Resources page: https://www.arteris.com/resources

Topics: semiconductor automotive neural networks AI AI chips flexnoc ai package VC-Links noc interconnect ML AI SoC Designers synchronous virtual channels

SemiWiki: Disturbances in the AI Force

Bernard Murphy (SemiWiki) reflects on a discussion with Kurt Shuler, VP Marketing at Arteris IP, on customer trends in design for advanced ML accelerators, why these look quite different from traditional processor architectures and the implication for design particularly around the NoC interconnect in this SemiWiki blog:

Disturbances in the AI Force

January 3rd, 2019 - By Bernard Murphy

In the normal evolution of specialized hardware IP functions, initial implementations start in academic research or R&D in big semiconductor companies, motivating new ventures specializing in functions of that type, who then either build critical mass to make it as a chip or IP supplier (such as Mobileye - initially) or get sucked into a larger chip or IP supplier (such as Intel or ARM or Synopsys). That was where hardware function ultimately settled, and many still do.

But recently the gravitational pull of mega-companies has distorted this normally straightforward evolution. In cloud services this list includes Amazon, Microsoft, Baidu and others. In smartphones you have Samsung, Huawei and Apple - yep, Huawei is ahead of Apple in smartphone shipments and is gunning to be #1. These companies, neither semiconductor nor IP, are big enough to do whatever they want to grab market share. What they do to further their goals in competition with the other giants can have a major impact on the evolution path for IP suppliers.

Arteris IP is closely involved with many of these companies, from Cambricon to Huawei/HiSilicon to Baidu to emerging companies like Lynxi, offering their network on chip (NoC) solutions with the AI package allowing for architecture tuning to the special needs of high-end NN designs. Check out more here; http://www.arteris.com/flexnoc-ai-package

Topics: NoC semiconductor semiwiki kurt shuler AI chips flexnoc ai package hardware ip accelerators noc interconnect

SemiWiki: On-Chip Networks at the Bleeding Edge of ML

On-chip networks become a lot more challenging at the high-end of machine learning (ML). Bernard Murphy (SemiWiki) talked with Kurt Shuler, VP Marketing at Arteris IP, about the experience they have developed over the years of working with well-known ML product builders and how this has influenced  the AI package recently released by Arteris IP in this SemiWiki blog:

On-Chip Networks at the Bleeding Edge of ML 

November 29th,  2018 - By Bernard Murphy

I wrote a while back about some of the more exotic architectures for machine learning (ML), especially for neural net (NN) training in the data center but also in some edge applications. In less hairy applications, we’re used to seeing CPU-based NNs at the low end, GPUs most commonly (and most widely known) in data centers as the workhorse for training, and for the early incarnations of some mobile apps (mobile AR/MR for example), FPGAs in applications where architecture/performance becomes more important but power isn’t super-constrained, DSPs in applications pushing performance per watt harder and custom designs such as the Google TPU pushing even harder.

Topics: SoC NoC FPGAs semiconductor machine learning FlexNoC semiwiki kurt shuler AI chips flexnoc ai package