Arteris Articles

Semiconductor Engineering: Optimizing NoC-Based Designs

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Semiconductor Engineering article:

Optimizing NoC-Based Designs

May 5th, 2022 - By Paul Graykowski

Further optimization of RTL repartitioning with switching from crossbar interconnects to NoCs.

Semiconductor development is currently in a phase of rapid evolution driven by the combination of new technologies and methodologies. The technique of combining multiple functions into systems-on-chips (SoCs) is continuing to grow in complexity. Rapid advancement in new technologies for market segments like data centers, robotics, ADAS and artificial intelligence/machine learning (AI/ML) are resulting in a new breed of SoCs. These fields demand designs that are maximized for both power and performance efficiency. Designers are finding that networks-on-chip (NoCs) provide the enabling technology to meet this demand and are accelerating the move away from crossbar interconnect technology.

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Topics: network-on-chip timing closure ADAS semiconductor engineering latency bandwidth SoCs congestion logic RTL data centers AI/ML NoCs floorplan Arteris IP (AIP) Paul Graykowski partitioning physical design crossbar interconnect robotics

Semiconductor Engineering: Data Explosion Pushes Boundaries of IC Interconnects

Benoit de Lescure, CTO at Arteris IP is quoted in this new article in Semiconductor Engineering:

Data Explosion Pushes Boundaries of IC Interconnects

September 22nd, 2021 - By Ann Steffora Mutschler

Design teams rethink the movement of data on-chip, off-chip, and between chips in a package.

“As chips become extremely large, the interconnect is touching all of the IP blocks in the chip. Benoit de Lescure, CTO at Arteris IP. “In this way, the interconnect is growing like the chip. Other components are not. A PCI controller will stay a PCI controller, but the interconnect size grows along with the size of the chip ,so there are scalability issues, especially because designing a good interconnect requires an understanding of how it will be implemented physically. How will it connect all those components on the chip? What amount of free space on the die will be left for the interconnect to use? What switch topology are you going to implement so that the physical aspects are easier later on? As the size of the problem grows bigger, it becomes significantly more difficult to come up with good interconnect decisions.”

Topics: Interconnect autonomous driving semiconductor engineering arteris ip Benoit de Lescure SoCs kurt shuler PHY scalability floorplan PCI controller switch topology D2D digital controller