Arteris Articles

Semiconductor Engineering: Time For FMEDA Reuse?

Stefano Lorenzini, Fellow & Functional Safety Manager at Arteris IP authored this Semiconductor Engineering article:

Time for FMEDA Reuse?

 July 7th, 2022 - By Stefano Lorenzini

Making it easier to integrate configurable IP into safety-critical systems.

How do designers quantify safety in electronic systems? Through one or more tables called Failure Modes, Effects and Diagnostic Analysis – FMEDA. In fact, an FMEDA does not have to be a table; it could be manifested in scripts or some other form, but a table is the easiest way to think of this information. Think of an FMEDA for an IP, as the concept extends easily to a system-on-chip (SoC). The table has a row for each failure mode that the IP experts can imagine might lead to a critical safety problem. Following identifying information for that failure mode is a description of the effect – the safety problem it might cause. Through fault simulation, the safety engineer determines the likelihood of the root cause problem leading to that effect. If the likelihood is significant, the designer will propose a mitigation technique, such as a parity check to detect the problem or an error-correcting code (ECC) check to correct it. A completed FMEDA then represents a comprehensive safety quality document for that IP, a characterization that an SoC integrator can use when determining the FMEDA for the whole design.

Learn more about Arteris IP Deployment Technology Products .

 

Topics: IP System-on-Chip functional safety network-on-chip semiconductor engineering SoCs FMEDA scalability traceability Stefano Lorenzini NoCs Arteris IP (AIP)

Electronic Design Article: Making ISO 26262 Traceability Practical


This Electronic Design article, 'Making ISO 26262 Traceability Practical', covers Arteris IP's Harmony Trace in this piece authored by Paul Graykowski, Senior Technical Marketing Manager. 

March 4 , 2021 - By Paul Graykowski

The ISO 26262 standard states that functional-safety assessors should consider if requirements management, including bidirectional traceability, is adequately implemented. The standard doesn’t specify how an assessor should go about accomplishing this task. However, it’s reasonable to assume that a limited subset of connections between requirements and implementation probably doesn’t rise to the expectation.

 

For more information about Arteris Harmony Trace please visit: https://www.arteris.com/harmony-trace-design-data-intelligence

 

Topics: NoC functional safety ISO 26262 network-on-chip autonomous vehicles ip-xact SoCs AI chips EDA electronic design traceability Arteris IP (AIP) Arteris Harmony Trace Paul Graykowski HSI PLM ALM

Semiconductor Engineering: Automotive Outlook: 2022

Kurt Shuler, VP of Marketing at Arteris IP is quoted in this Semiconductor Engineering article:

Automotive Outlook: 2022

January 7th, 2022 - By Ann Steffora Mutschler

Short-term IC supply-chain problems and long-term architectural and business changes top the list of what's ahead.


“Here, initially it was algorithms and AI or machine learning on visual inputs. Then, lidar and radar data was added to that in a sensor fusion function. That is then overlaid with mapping. This means even more hardware architectures are driven by the needs of the software," said Kurt Shuler, vice president of marketing at Arteris IP.

Topics: functional safety ISO 26262 network-on-chip automotive ADAS machine learning mobileye semiconductor engineering AI arteris ip LIDAR SoCs EDA 5G Tier 1s NoCs Tesla Arteris IP (AIP)

EDN: How NoCs Ace Power Management and Functional Safety in SoCs

Benoit de Lescure, CTO at Arteris IP authors this 3rd article in a new series for EDN:

How NoCs Ace Power Management and Functional Safety in SoCs

September 15th, 2021 - By Benoit de Lescure

The NoC interconnect is the SoC architecture.

This third article highlights how NoC technology provides capabilities like power management and functional safety that are not possible with older crossbar-based interconnect technologies. For design teams creating modern SoCs, whether large datacenter AI accelerators or power-sipping IoT sensors, NoC interconnect technology is key to implementing these SoC architectures and optimizing the dataflow within them.

To catch up on the first and second articles in this series, click below:

Topics: ARM NIC-400 SoC NoC functional safety network-on-chip crossbar automotive AI arteris ip Benoit de Lescure interconnects EDN LBIST Design Management Power Management Semiconductors DVSF