Arteris Articles

Semiconductor Engineering: Domain-Specific Memory

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Domain-Specific Memory

March 11th, 2021 - By Brian Bailey

Rethinking fundamental approaches to memory could have a huge impact on performance.

“Remember video memories — DRAM with built-in shift registers?” asks Michael Frank, fellow and system architect at Arteris IP. “Perhaps GDDR [1-5], special cache tag memories, or associative memories back in the days of TTL? A lot of these have not really survived because their functionality was too specific. They targeted a unique device. You need a large enough domain, and you are fighting against the low cost of today’s DRAM, which has the benefit of high volume and large-scale manufacturing.”

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip GPUs cache DRAM interconnects Michael Frank HBM

Forbes Technology Council: AI and the Third Wave of Silicon Processors

Ty Garibay, CTO at Arteris IP, authors this article for Forbes Technology Council:

Topics: interconnect IP Systems-on-Chip ArterisIP flexnoc interconnect AI GPUs ips Forbes

SemiWiki: Safety in the Interconnect

Kurt Shuler, VP of Marketing at Arteris IP, chats with Bernard Murphy in this SemiWiki blog:

Safety in the Interconnect


April 26th,  2018 - By Bernard Murphy

Bernard Murphy (SemiWiki) provides his take on a talk by Kurt Shuler how safety assurance extends to the interconnect, particular challenges in meeting ISO 26262 requirements for highly configurable IP and how Arteris IP addresses these challenges for users of their NoC systems.

Topics: SoC on-chip interconnect networks CPUs GPUs FMEA NIU system safety assurance semiwiki critical safety BIST