Arteris Articles

Semiconductor Engineering: Steep Spike For Chip Complexity And Unknowns

K. Charles Janac, CEO at Arteris IP is quoted in this new Semiconductor Engineering article:

Steep Spike For Chip Complexity And Unknowns

May 5th, 2021 - By Ed Sperling

Increased interactions and customizations drive up risk of re-spins or failures.

“There are several aspects that need to be considered, such as making sure the customer is using the right version of the IP,” said K. Charles Janac, chairman and CEO of Arteris IP. “You’re basically enforcing that the IP-XACT parameters are there in order for the IP block to be admitted into the SoC. There’s also the aspect of supply management. Many of these companies have a layout house, a design house, and foundry contractors. If that entire supply chain is IP-XACT — from the interaction between the various parties in the supply chain to what ultimately provide what goes into the SoC — it gets much, much smoother. At the same time, you are going to have some pieces of the chip that are on the leading-edge process and some on the trailing edge, such as analog.

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip K. Charles Janac ip-xact interconnects chiplets inter-chip IPD