Arteris Articles

EDN: How NoCs Ace Power Management and Functional Safety in SoCs

Benoit de Lescure, CTO at Arteris IP authors this 3rd article in a new series for EDN:

How NoCs Ace Power Management and Functional Safety in SoCs

September 15th, 2021 - By Benoit de Lescure

The NoC interconnect is the SoC architecture.

This third article highlights how NoC technology provides capabilities like power management and functional safety that are not possible with older crossbar-based interconnect technologies. For design teams creating modern SoCs, whether large datacenter AI accelerators or power-sipping IoT sensors, NoC interconnect technology is key to implementing these SoC architectures and optimizing the dataflow within them.

To catch up on the first and second articles in this series, click below:

Topics: ARM NIC-400 SoC NoC functional safety network-on-chip crossbar automotive AI arteris ip Benoit de Lescure interconnects EDN LBIST Design Management Power Management Semiconductors DVSF

Semiconductor Engineering: Shifting Toward Data-Driven Chip Architectures

K. Charles Janac, CEO at Arteris IP is quoted in this new article in Semiconductor Engineering:

Shifting Toward Data-Driven Chip Architectures

June 16th, 2021 - By Ed Sperling and Ann Steffora Mutschler

Rethinking how to improve performance and lower power in semiconductors.

“There are dynamic routing opportunities at runtime,” said K. Charles Janac, chairman and CEO of Arteris IP. “We’ve always resisted runtime dynamic routing because there are issues with verification. If you have billions of transactions, the verification is much simpler if you’re forcing the traffic to go onto a single connection every time. But there are opportunities for easing that in the future and have the NoC essentially be able to reroute traffic dynamically based on some sort of routing controller, which in turn is controlled by some global software."

Topics: SoC NoC network-on-chip automotive machine learning semiconductor engineering arteris ip verification K. Charles Janac interconnects datacenters

Semiconductor Engineering: Big Changes Ahead For Connected Vehicles

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

Big Changes Ahead For Connected Vehicles

June 3rd, 2021 - By Ann Steffora Mutschler

Tapping into multiple services, both inside and outside a car, requires a rethinking of everything from architectures to security.

“When you look at the geography of the car, you have to consider how to chop things up,” said Kurt Shuler, vice president of marketing at Arteris IP. “As part of the ECU consolidation discussion, zonal can be one approach such that, for example, ‘the antilock braking system is usually next to this other subsystem, so let’s put those together, and we’ll make that one electronic system that’ll cover all that stuff.’ However, there are still some who say all of this is going to go together, like a centralized architecture where there is a common brain, which makes sense from a functional safety and redundancy standpoint.”

Topics: SoC NoC network-on-chip automotive semiconductor engineering arteris ip interconnects Tier-1 automotive supplier automotive OEMs ECUs service-oriented architectures SOAs zonal architectures Tier 2

Semiconductor Engineering: Automotive AI Hardware: A New Breed

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article in Semiconductor Engineering:

Automotive AI Hardware: A New Breed

June 3rd, 2021 - By Kurt Shuler

What sets automotive apart from the conventional wisdom on AI hardware markets.

Arteris IP functional safety manager Stefano Lorenzini recently presented “Automotive Systems-on-Chip (SoCs) with AI/ML and Functional Safety” at the Linley Processor Conference. A main point of the presentation was that conventional wisdom on AI hardware markets is binary. There’s AI in the cloud: Big, power-hungry, general-purpose. And there’s AI at the edge: Small, low power, limited application-specific features. Automotive AI doesn’t really fit into either category. To power ADAS and autonomous driving functions, these chips are extremely application-specific and require more performance than typical edge AI, are low power but not as low as IoT chips at the edge, and must be as low cost as possible. They also add a new angle – low latency because safety demands fast and deterministic response times. Add to all that the functional safety requirements demanded by ISO 26262 – inside the AI structure as much as everywhere else. Bottom line: Automotive AI SoC architectures are unique beasts.

Topics: SoC NoC functional safety network-on-chip automotive ECC The Linley Group ISO 26262 compliance semiconductor engineering arteris ip interconnects kurt shuler AI SoCs AI/ML Stefano Lorenzini heterogeneous socs ASIL