Arteris Articles

Arteris IP Has a New Updated Website!

Arteris IP has a new website!

Topics: SoC NoC ArterisIP noc interconnect ML/AI IP market SoC IP chip design ip deployment

EDA Cafe: Arteris IP Extends IP-XACT to UVM Testbenches

Vincent Thibaut, Director of IP Deployment Product Strategy at Arteris IP authored this new article for EDA Cafe:

Arteris IP Extends IP-XACT to UVM Testbenches

July 2, 2021 - By Vincent Thibaut


To be clear, the goal here is not to autogenerate the internals of the complex test sequences. However, the IP-XACT platform from Arteris IP does handle register sequences. Instead, view the universal verification methodology (UVM) testbench as part of an assembly of the device under test (DUT), plus many complex VIPs. IP-XACT lends itself nicely to this concept. To be effective, packaging needs several extensions so that configuration can be managed from the IP-XACT level. Testbenches will be challenged to include more and more VIPs as design complexity grows. There are compelling reasons to explore IP-XACT packaging for VIPs.

Topics: SoC NoC arteris ip verification ip-xact UVM ip deployment IPD testbench assembly DUT SoC testbenches vincent thibaut VIPs UVM testbenches

Semiconductor Engineering: SoC Integration Complexity: Size Doesn't (Always) Matter

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new Semiconductor Engineering article:

SoC Integration Complexity: Size Doesn't (Always) Matter

April 1st, 2021 - By Kurt Shuler

Even small IoT designs can have plenty of complexity in architecture and integration.

It’s common when talking about complexity in systems-on-chip (SoCs) to haul out monster examples: application processors, giant AI chips, and the like. Breaking with that tradition, consider an internet of things (IoT) design, which can still challenge engineers with plenty of complexity in architecture and integration. This complexity springs from two drivers: very low power consumption, even using harvested MEMS power instead of a battery, and quick turnaround to build out a huge family of products based on a common SoC platform while keeping tight control on development and unit costs.

Topics: SoC NoC network-on-chip IoT low power semiconductor engineering arteris ip ip-xact interconnects kurt shuler DVFS ip deployment