Arteris IP has a new website!
Madelyn Miller, on Wed, Jul 07, 2021 @ 06:00 AM
Vincent Thibaut, Director of IP Deployment Product Strategy at Arteris IP authored this new article for EDA Cafe:
July 2, 2021 - By Vincent Thibaut
To be clear, the goal here is not to autogenerate the internals of the complex test sequences. However, the IP-XACT platform from Arteris IP does handle register sequences. Instead, view the universal verification methodology (UVM) testbench as part of an assembly of the device under test (DUT), plus many complex VIPs. IP-XACT lends itself nicely to this concept. To be effective, packaging needs several extensions so that configuration can be managed from the IP-XACT level. Testbenches will be challenged to include more and more VIPs as design complexity grows. There are compelling reasons to explore IP-XACT packaging for VIPs.
Madelyn Miller, on Thu, Apr 01, 2021 @ 09:30 AM
Kurt Shuler, Vice President of Marketing at Arteris IP authored this new Semiconductor Engineering article:
April 1st, 2021 - By Kurt Shuler
Even small IoT designs can have plenty of complexity in architecture and integration.
It’s common when talking about complexity in systems-on-chip (SoCs) to haul out monster examples: application processors, giant AI chips, and the like. Breaking with that tradition, consider an internet of things (IoT) design, which can still challenge engineers with plenty of complexity in architecture and integration. This complexity springs from two drivers: very low power consumption, even using harvested MEMS power instead of a battery, and quick turnaround to build out a huge family of products based on a common SoC platform while keeping tight control on development and unit costs.