Arteris Articles

Arteris IP Has a New Updated Website!

Arteris IP has a new website!

Topics: SoC NoC ArterisIP noc interconnect ML/AI IP market SoC IP chip design ip deployment

Semiconductor Engineering: Learning ISO 26262 - 2nd Edition

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article on the interpretation of ISO 26262 in today's Semiconductor Engineering blog:

Learning ISO 26262 -2nd Edition 

December 7th, 2020 - By Kurt Shuler

Interpreting the functional safety standard isn't as simple as just looking at the document.

Ambiguity is a feature, not a bug!

Why? Partly ambiguity. Because what I think is clear, you may not think is clear. And some of this ambiguity is intentional: This is a voluntary (thought widely followed) standard, aiming to preserve flexibility for innovation and differentiation. The committees don't want to be too prescriptive, which inevitably leads to some ambiguity.

Topics: SoC NoC functional safety ISO 26262 automotive semiconductor engineering Soft IP FMEA kurt shuler OEMs FMEDA noc interconnect IP market Part 11 tailoring safety element standards SEooC

Semiconductor Engineering: Using ICs To Shrink Auto's Carbon Footprint

Guillaume Boillet, Director of Product Management at Arteris IP is quoted in this new article in Semiconductor Engineering:

Using ICs To Shrink Auto's Carbon Footprint

December 3rd, 2020 - By Ann Steffora Mutschler

How chips will play an increasingly vital role in improving efficiency of cars and infrastructure.

Eliminating or reducing redundancy can help, as well. While cars are truly becoming supercomputers on wheels, at the same time there’s less redundancy. “There’s more compute power, but it’s compensated by systems that are more elegant,” said Guillaume Boillet, director of product management at Arteris IP. “There is rationalization of the traffic, and of course, as the technology improves, over time the chips consume less and less, so it’s a balancing act.”

Topics: SoC NoC automotive semiconductor engineering noc interconnect 5G IP market electric vehicles

Semiconductor Engineering: Is Hardware-Assisted Verification Avoidable?

Khaled Labib, Vice President of Engineering at Arteris IP is quoted in this new article in Semiconductor Engineering:

Is Hardware-Assisted Verification Avoidable?

October 28th, 2020 - By Brian Bailey

Simulation is no longer up to the task of system-level verification, but making the switch to hardware-assisted verification can lead to some surprises if you do not fully plan ahead.

Bringing hardware-assisted verification in for the first time is not easy. “For a small company, emulation systems are expensive,” says Arteris’ Labib. “The ones with more advanced features run you about a million dollars for an average starting configuration. If you want to start lower than that, you’re going to have to either give up on features or go with a smaller commercial configuration. But this has become critical to our business, and even as a small company we had to find the necessary budget to buy emulation.”

Topics: SoC NoC semiconductor engineering interconnects emulation noc interconnect IP market cloud khaled labib testbench configurable IP solution regression