Arteris Articles

Semiconductor Engineering: Automotive Outlook: 2022

Kurt Shuler, VP of Marketing at Arteris IP is quoted in this Semiconductor Engineering article:

Automotive Outlook: 2022

January 7th, 2022 - By Ann Steffora Mutschler

Short-term IC supply-chain problems and long-term architectural and business changes top the list of what's ahead.

“Here, initially it was algorithms and AI or machine learning on visual inputs. Then, lidar and radar data was added to that in a sensor fusion function. That is then overlaid with mapping. This means even more hardware architectures are driven by the needs of the software," said Kurt Shuler, vice president of marketing at Arteris IP.

Topics: functional safety ISO 26262 network-on-chip automotive ADAS machine learning mobileye semiconductor engineering AI arteris ip LIDAR SoCs EDA 5G Tier 1s NoCs Tesla Arteris IP (AIP)

Semiconductor Engineering: Amdahl Limits On AI

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new with Semiconductor Engineering article:

Amdahl Limits On AI

December 9th, 2021 - By Brian Bailey

The application of old techniques to new problems only gets you so far. To remove limitations in AI processors, new thinking is required.

“If you can’t parallelize a section, the serial section determines the maximum speed up,” says Michael Frank, fellow and system architect at Arteris IP. “If you assume that you can parallelize infinitely at times, the parallel section becomes limited by the bandwidth that you have available in the system. So there is a maximum that I can parallelize, because I run out of bandwidth.”

Topics: network-on-chip machine learning artificial intelligence semiconductor engineering arteris ip SoCs NoCs Arteris IP (AIP) RISC-V on-chip cache memory bandwidth

Semiconductor Engineering: Shifting Toward Data-Driven Chip Architectures

K. Charles Janac, CEO at Arteris IP is quoted in this new article in Semiconductor Engineering:

Shifting Toward Data-Driven Chip Architectures

June 16th, 2021 - By Ed Sperling and Ann Steffora Mutschler

Rethinking how to improve performance and lower power in semiconductors.

“There are dynamic routing opportunities at runtime,” said K. Charles Janac, chairman and CEO of Arteris IP. “We’ve always resisted runtime dynamic routing because there are issues with verification. If you have billions of transactions, the verification is much simpler if you’re forcing the traffic to go onto a single connection every time. But there are opportunities for easing that in the future and have the NoC essentially be able to reroute traffic dynamically based on some sort of routing controller, which in turn is controlled by some global software."

Topics: SoC NoC network-on-chip automotive machine learning semiconductor engineering arteris ip verification K. Charles Janac interconnects datacenters

Semiconductor Engineering: Power Optimization: What's Next?

Guillaume Boillet, Director of Product Management at Arteris IP is quoted in this new article in Semiconductor Engineering:

Power Optimization: What's Next!

May 17th, 2021 - By Brian Bailey

Clock gating and power gating were a good start, but there is much more that can and should be done to minimize power.

“The efforts in terms of methodology, compute resources and engineering talent to deploy system-level techniques are definitely non-negligible,” says Guillaume Boillet, director of product management for Arteris IP. “Only the most advanced and power-savvy design teams invest in those.”

Topics: SoC NoC network-on-chip dynamic power machine learning semiconductor engineering arteris ip interconnects RTL Guillaume Boillet clock-gating macro-level