Arteris Articles

SemiWiki: AI, Safety and Low Power, Compounding Complexity

Bernard Murphy talked to Kurt Shuler about the complexities of combining low power, safety and AI constraints in a design. Design challenges have evolved beyond PPA to encompass new constraints but these are still manageable, with the right architecture in this new SemiWiki blog:

AI, Safety and Low Power, Compounding Complexity 

April 28th, 2020 - By Bernard Murphy

The nexus of complexity in SoC design these days has to be in automotive ADAS devices. Arteris IP highlighted this in the Linley Processor Conference recently where they talked about an ADAS chip that Toshiba had built. This has multiple vision and AI accelerators, both DSP and DNN-based. It is clearly aiming for ISO 26262 ASIL D certification since the design separates a safety island from the processing island, pretty much the only way you can get to ASIL D in a heterogenous mix of ASIL-level on-chip subsystems. Equally clear, it’s aiming to run at low power – around 2.7W for the processing island (the bulk of the functionality). It’s all very well to be smart but when you have dozens of smart components scattered around the car, that adds up to a lot of power consumption. The car isn’t going to be very smart if it runs its battery flat.


Topics: SoC ISO 26262 semiconductor Toshiba ADAS Ncore FlexNoC AI semiwiki ASIL D noc interconnect memory hierarchy

SemiWiki: That Last Level Cache is Pretty Important

Bernard Murphy talked to Kurt Shuler to get an update on the Arteris IP CodaCache IP. That led to some insights not just on what has changed but also why last level cache is so important in this new SemiWiki blog:

That Last Level Cache is Pretty Important

April 21st, 2020 - By Bernard Murphy

Last-level cache seemed to me like one of those, yeah I get it, but sort of obscure technical corners that only uber-geek cache specialists would care about. Then I stumbled on an AnandTech review on the iPhone 11 Pro and Max and started to understand that this contributes to more than just engineering satisfaction.

For more information, please download this paper:

Topics: SoC ISO 26262 semiconductor ArterisIP AI semiwiki last level cache kurt shuler noc interconnect memory hierarchy Coda Cache LLC

Semiconductor Engineering: Last-Level Cache Video

Tech Talk Video: Last-Level Cache 

April 6th, 2020 - By Ed Sperling

Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources.

Topics: network-on-chip semiconductor CodaCache tech talk video on-chip memory data centers memory hierarchy semiengineering

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