Arteris Articles

Semiconductor Engineering: Many Chiplet Challenges Ahead

Michael Frank, fellow and system architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Many Chiplet Challenges Ahead

April 12th, 2021 - By Brian Bailey

Assembling systems from physical IP gaining mindshare, but there are technical, business and logistical issues that need to be resolved before this will work.

“The size of the bits and pieces is an issue,” says Michael Frank, fellow and system architect at Arteris IP. “It is perhaps less of an issue with chiplets or 2.5D, where things are mounted on a substrate, but it adds additional challenges for 3D. We are no longer dealing with gravel. It is grains of sand, or even dust specs. It’s more robust to build boards.”

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip interconnects chiplets Michael Frank 5nm ESD

Semiconductor Engineering: More Data Drives Focus On IC Energy Efficiency

Michael Frank, fellow and system architect at Arteris IP are quoted in this new Semiconductor Engineering article:

More Data Drives Focus On IC Energy Efficiency

April 8th, 2021 - By Ann Steffora Mutschler

Decisions that affect how, when, and where data gets processed.

"On the chip side, it’s an engineering discipline. On the other side are the algorithm experts who understand what the masks are and what they want to do,” said Michael Frank, fellow and system architect at Arteris IP.

Topics: SoC NoC network-on-chip machine learning neural networks semiconductor engineering arteris ip interconnects chiplets Michael Frank memory architecture TensorFlow

Semiconductor Engineering: Domain-Specific Memory

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Domain-Specific Memory

March 11th, 2021 - By Brian Bailey

Rethinking fundamental approaches to memory could have a huge impact on performance.

“Remember video memories — DRAM with built-in shift registers?” asks Michael Frank, fellow and system architect at Arteris IP. “Perhaps GDDR [1-5], special cache tag memories, or associative memories back in the days of TTL? A lot of these have not really survived because their functionality was too specific. They targeted a unique device. You need a large enough domain, and you are fighting against the low cost of today’s DRAM, which has the benefit of high volume and large-scale manufacturing.”

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip GPUs cache DRAM interconnects Michael Frank HBM

Semiconductor Engineering: Chiplets For The Masses

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Chiplets for The Masses

March 3rd, 2021 - By Brian Bailey

Chiplets are technically and commercially viable, but not yet accessible to the majority of the market. How does the ecosystem get established?

“I look at the pictures of Intel’s new chips, and it turns out there are eight compute tiles that could be called chiplets, put together with some strips in the middle that contain cache and interconnect tiles,” says Michael Frank, fellow and system architect at Arteris IP. “And it is all sitting on a silicon substrate. There are clearly places where it is worth the money, and worth the efforts. But this paradigm has to be built on standards. It needs to cover the electrical properties, communications, physical attributes, etc. You cannot build different chiplets for every company. No matter how you look at it, it is still a chip and you have to go through all the steps you normally would for a tape-out.”

Topics: SoC NoC network-on-chip moore's law semiconductor engineering arteris ip cache interconnects intel Michael Frank chips alliance darpa