Hezi Saar (Synopsys' M-PHY PM), Philippe Martin (Arteris Senior Fellow and LLI God) and I will be hosting an EE Times webinar on the MIPI Low Latency Interface (MIPI LLI) and M-PHY on Wednesday, 27 June, at 9 am Pacific time.
Kurt Shuler, on Fri, Jun 22, 2012 @ 04:40 PM
Hezi Saar (Synopsys' M-PHY PM), Philippe Martin (Arteris Senior Fellow and LLI God) and I will be hosting an EE Times webinar on the MIPI Low Latency Interface (MIPI LLI) and M-PHY on Wednesday, 27 June, at 9 am Pacific time.
Kurt Shuler, on Thu, May 17, 2012 @ 09:07 AM
I've received a lot of feedback on the "Interchip Connectivity: HSIC, UniPro, HSI, C2C, LLI...oh my!" article I wrote last year and I thank everyone for their feedback!
Kurt Shuler, on Thu, Feb 23, 2012 @ 09:34 AM
It may seem strange to link two interchip interface standards to the future of 3D integrated circuits, but please bear with me for a few minutes. I hope to prove that the learning from today will impact how we design SoCs in the near future.
Kurt Shuler, on Tue, Jan 17, 2012 @ 11:07 AM
Two new options for interchip connectivity are available today that enable sharing a DRAM memory between two chips for data and programs. These standards, called MIPI Low Latency Interface (MIPI LLI) and Chip-to-Chip (C2C), are primarily targeted at mobile phones, where a mobile phone’s modem usually requires its own discreet DRAM. With either C2C or MIPI LLI, the mobile phone modem can use the application processor’s DRAM though a low-latency, memory-mapped connection that requires no software drivers or runtime software.