Arteris Articles

Semiconductor Engineering: More Data Drives Focus On IC Energy Efficiency

Michael Frank, fellow and system architect at Arteris IP are quoted in this new Semiconductor Engineering article:

More Data Drives Focus On IC Energy Efficiency

April 8th, 2021 - By Ann Steffora Mutschler

Decisions that affect how, when, and where data gets processed.

"On the chip side, it’s an engineering discipline. On the other side are the algorithm experts who understand what the masks are and what they want to do,” said Michael Frank, fellow and system architect at Arteris IP.

Topics: SoC NoC network-on-chip machine learning neural networks semiconductor engineering arteris ip interconnects chiplets Michael Frank memory architecture TensorFlow

Semiconductor Engineering: Interconnects In A Domain-Specific World

Kurt Shuler, Vice President of Marketing and Guillaume Boillet, Director of Product Management at Arteris IP are quoted in this new Semiconductor Engineering article:

Interconnects In A Domain-Specific World

April 8th, 2021 - By Brian Bailey

When and where tradeoffs between efficiency and flexibility make sense.

"The prediction of power consumption of chips under a given workload is one of the most complex tasks our industry must tackle today,” says Guillaume Boillet, director of product management for Arteris IP

Kurt Shuler, vice president of marketing at Arteris IP says, “You may have 200 things connected to your NoC at the center of the chip. The NoC tool manages all of the meta data for the IP connected to it. Back-figuring all that information is a huge source of systematic errors. We all make mistakes. And that causes problems, not just for regular chips. But can you imagine that for typical functional safety requirements?”

Topics: SoC NoC functional safety network-on-chip neural networks semiconductor engineering arteris ip interconnects kurt shuler power consumption meta data

Semiconductor Engineering: Von Neumann Is Struggling

Michael Frank, Fellow and System Architect at Arteris IP is quoted in today's Semiconductor Engineering blog:

Von Neumann Is Struggling

January 18th, 2021 - By Brian Bailey

The backbone of computing architecture for 75 years is being supplanted by more efficient, less general compute architecture.

“One of the problems is that CPUs are not really good at anything,” says Michael Frank, fellow and system architect at Arteris IP. “CPUs are good at processing a single thread that has a lot of decisions in it. That is why you have branch predictors, and they have been the subject of research for many years.”

Topics: SoC Interconnect NoC network-on-chip memory CPU neural networks semiconductor engineering accelerators chip architectures

Semiconductor Engineering: Spiking Neural Networks: Research Projects or Commercial Products?

Michael Frank, fellow and chief architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Spiking Neural Networks: Research Projects or Commercial Products?

May 18th, 2020 - By Byron Moyer

Opinions differ widely, but in this space that isn't unusual.
 
SNN neurons typically are implemented in one of two ways. The approaches are motivated by analog implementations, although they can be abstracted into digital equivalents.  Arteris IP   fellow and chief architect Michael Frank refers to this as “emulation.” He points to several challenges for an analog implementation: “With analog, you would need to customize the model to the specific chip for inference. No two transistors are the same. And at 7 nm, you can’t do analog.”
 
Topics: analog SoC automotive neural networks NoC technology semiconductor engineering emulation noc interconnect IP market SNN multi-cast spike data