Arteris Articles

Semiconductor Engineering: Von Neumann Is Struggling

Michael Frank, Fellow and System Architect at Arteris IP is quoted in today's Semiconductor Engineering blog:

Von Neumann Is Struggling

January 18th, 2021 - By Brian Bailey

The backbone of computing architecture for 75 years is being supplanted by more efficient, less general compute architecture.

“One of the problems is that CPUs are not really good at anything,” says Michael Frank, fellow and system architect at Arteris IP. “CPUs are good at processing a single thread that has a lot of decisions in it. That is why you have branch predictors, and they have been the subject of research for many years.”

Topics: SoC Interconnect NoC network-on-chip memory CPU neural networks semiconductor engineering accelerators chip architectures

Semiconductor Engineering: Spiking Neural Networks: Research Projects or Commercial Products?

Michael Frank, fellow and chief architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Spiking Neural Networks: Research Projects or Commercial Products?

May 18th, 2020 - By Byron Moyer

Opinions differ widely, but in this space that isn't unusual.
 
SNN neurons typically are implemented in one of two ways. The approaches are motivated by analog implementations, although they can be abstracted into digital equivalents.  Arteris IP   fellow and chief architect Michael Frank refers to this as “emulation.” He points to several challenges for an analog implementation: “With analog, you would need to customize the model to the specific chip for inference. No two transistors are the same. And at 7 nm, you can’t do analog.”
 
Topics: analog SoC automotive neural networks NoC technology semiconductor engineering emulation noc interconnect IP market SNN multi-cast spike data

Semiconductor Engineering: Tech Talk - CXL vs. CCIX Video

Tech Talk Video: CXL vs. CCIX 


March 11,  2020 - By Ed Sperling

Ed Sperling interviews Kurt Shuler at Arteris IP headquarters about the differences between CXL and CCIX.

Arteris IP’s Kurt Shuler talks about how these two standards differ, which one works best where, and what each was designed for.

Topics: semiconductor IoT automotive CCIX neural networks AI tech talk video CXL

Semiconductor Engineering: The Race To Multi-Domain SoCs

 Arteris IP's CEO looks at how automotive and AI are Altering chip design in this article in Semiconductor Engineering;

The Race To Multi-Domain SoCs

February 7th,  2019 - By Ed Sperling

K. Charles Janac, president and CEO of Arteris IP, sat
down with Semiconductor Engineering to discuss the impact of automotive and AI on chip design. What follows are excerpts of that conversation.

SE: What do you see as the biggest changes over the next 12 to 24 months?
Janac: There are segments of the semiconductor market that are shrinking, such as DTV and simple IoT. Others are going through an investment phase, including automotive, AI/machine learning and China. You really want to be focused on those segments. 

SE: So does IP that’s being developed today look radically different than it did five years ago?
Janac:
Yes, everything is getting amazingly complex. What people are building right now are multi-domain SoCs. The CPU, which used to do all the work, does relatively less work. There are accelerators for vision and data analysis outside of the CPU subsystem. There are machine learning sections, some general-purpose, some very specific, all on-chip. There is a memory subsystem with very high-bandwidth memory and low latency. There also is functional safety. You need tremendous performance because a car is a supercomputer on wheels. The car has to be very efficient, because you need to deliver that compute power without water cooling. Power management becomes very sophisticated. And then there are functional safety and security subsystems to keep these safe from environmental and man-made issues.

SE: Where does the network on chip (NoC) fit into all of this?
Janac: All data goes through the NoC of the chip. There are opportunities for generating value from that. But the increase in complexity is increasing the number and sophistication of the interconnect parts of the chip. Before, you may have had networks on chip. Now you may have 20 or 30.

Topics: semiconductor automotive ADAS neural networks AI LIDAR flexnoc ai package noc interconnect ML AI SoC Designers chiplets