Arteris Articles

EE Times article, AI Startups Plateau, AI SoCs Soar, and the Edge Diverges

Laurent Moll, Chief Operating Officer at Arteris IP, sits down with Junko Yoshida in this new EE Times article.

May 13th, 2021 - by Junko Yoshida

Laurent Moll, chief operating officer at Arteris, predicts that in the future, “everyone has some kind of AI in their SoCs.” That is good news for Arteris, because its business is in helping companies (large and small, or new and old) integrate SoCs by providing network-on-chip (NoC) IP and IP development tools.

Topics: semiconductor ADAS eetimes AI SoCs AI chips data centers noc interconnect smartphones SoC IP hyperscalers googles TPU car OEMS edge ai

SemiWiki: Arteris IP Contributes to Major MPSoC Text

Bernard Murphy of (SemiWiki) comments on a recent book release on MPSoC design. 

Arteris IP Contributes to Major MPSoC Text

April 29th, 2021 - Bernard Murphy

You might have heard of the Multicore and Multiprocessor SoC (MPSoC) Forum sponsored by IEEE and other industry associations and companies. This group of top-notch academic and industry technical leaders gets together once a year to talk about hardware and software architecture and applications for multicore and multiprocessor systems-on-chip (SoCs). They gather to debate the latest and greatest ideas to meet emerging needs.
 
K. Charles Janac, president and CEO of Arteris IP, wrote the first chapter in the third section on network-on-chip (NoC) architectures. I’m impressed that what must be considered a definitive technical reference on MPSoCs required a chapter on NoC interconnect, and the editors turned to Arteris IP to write that chapter.
Topics: SoC NoC ISO 26262 network-on-chip semiconductor AI semiwiki K. Charles Janac kurt shuler noc interconnect cache coherence MPSoC Forum

SemiWiki: SoC Integration - Predictable, Repeatable, Scalable

Bernard Murphy (SemiWiki) gets an update from Kurt Shuler, vice president of Marketing at Arteris IP on the benefits of integrating SoC data and NoC integration. 

SoC Integration - Predictable, Repeatable, Scalable

March 24th, 2021 - Bernard Murphy

On its face System-on-chip (SoC) integration doesn’t seem so hard. You gather and configure all the intellectual properties (IPs) you’re going to need, then stitch them together. Something you could delegate to new college hires, maybe? But it isn’t that simple. What makes SoC integration challenging is that there are so many parts including IPs and connections. Some are moving parts, changing as bugs are fixed. Some, like the interconnect, can only be completely defined when you integrate. There’s a lot of interdependence between these parts. Make a small change like importing a new revision of an IP or adapting to a spec tweak, and the consequences can ripple through your integration, not a big deal, perhaps, early in design. But a very big deal when you’ve finally wrestled hundreds of IPs and tens of thousands of connections into behaving. Then you have to drop in a couple more changes. Surely there’s a better way? Kurt Shuler shares his views on the need.
Topics: SoC NoC network-on-chip semiconductor FlexNoC semiwiki safety XML ip-xact magillem kurt shuler QoS noc interconnect EDA data integration traceability configuration software interface documentation enterprise

EE Times article, "Licensing Interconnect IP for Fun & Profit"

Kurt Shuler, VP Marketing at Arteris IP, authored this EE Times article discussing NoC interconnect Build or Buy.

February 25, 2021 - by Kurt Shuler

Why do we buy instead of build? Because the guys at the factory know what they’re doing.

The big question then becomes, which parts do we design in-house, and which do we bring in from outside? That’s a whiteboard architectural discussion, which can be heated and emotional. Engineers want to build stuff — that’s what they do. Managers want to get a working product out the door as economically as possible — that’s what they do. If the engineers want to make, and the managers want to buy, who wins? Who gets to make that call, and how do they justify the decision? 

Topics: SoC economics semiconductor eetimes AI SoCs RTL kurt shuler noc interconnect ML/AI SoC IP R&D costs buy vs build build vs buy