Arteris Articles

EDA Cafe: Arteris IP Extends IP-XACT to UVM Testbenches

Vincent Thibaut, Director of IP Deployment Product Strategy at Arteris IP authored this new article for EDA Cafe:

Arteris IP Extends IP-XACT to UVM Testbenches

July 2, 2021 - By Vincent Thibaut


To be clear, the goal here is not to autogenerate the internals of the complex test sequences. However, the IP-XACT platform from Arteris IP does handle register sequences. Instead, view the universal verification methodology (UVM) testbench as part of an assembly of the device under test (DUT), plus many complex VIPs. IP-XACT lends itself nicely to this concept. To be effective, packaging needs several extensions so that configuration can be managed from the IP-XACT level. Testbenches will be challenged to include more and more VIPs as design complexity grows. There are compelling reasons to explore IP-XACT packaging for VIPs.

Topics: SoC NoC arteris ip verification ip-xact UVM ip deployment IPD testbench assembly DUT SoC testbenches vincent thibaut VIPs UVM testbenches

Semiconductor Engineering: New Design Approaches For Automotive

Kurt Shuler, VP of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

New Design Approaches For Automotive

July 1st, 2021 - By Ann Steffora Mutschler

OEMs steer toward executable specs using model-based systems engineering.


“If you’re creating an anti-lock braking system or a windshield washer or something like that, it’s relatively simple and you don’t have to spend much time with these tools to be able to come up with that model,” said Kurt Shuler, vice president of marketing at Arteris IP. “But once you get to something really complex like a system on chip — just like with creating SystemC models or the like — you could spend more time than you would on the RTL, or on writing the specs for the RTL, the requirements and use cases for the specs for the RTL, or a SysML model.”

Topics: SoC NoC ISO 26262 ArterisIP SystemC semiconductor engineering arteris ip RTL kurt shuler SoC assembly SysML MBSE

Semiconductor Engineering: Shifting Toward Data-Driven Chip Architectures

K. Charles Janac, CEO at Arteris IP is quoted in this new article in Semiconductor Engineering:

Shifting Toward Data-Driven Chip Architectures

June 16th, 2021 - By Ed Sperling and Ann Steffora Mutschler

Rethinking how to improve performance and lower power in semiconductors.

“There are dynamic routing opportunities at runtime,” said K. Charles Janac, chairman and CEO of Arteris IP. “We’ve always resisted runtime dynamic routing because there are issues with verification. If you have billions of transactions, the verification is much simpler if you’re forcing the traffic to go onto a single connection every time. But there are opportunities for easing that in the future and have the NoC essentially be able to reroute traffic dynamically based on some sort of routing controller, which in turn is controlled by some global software."

Topics: SoC NoC network-on-chip automotive machine learning semiconductor engineering arteris ip verification K. Charles Janac interconnects datacenters

Semiconductor Engineering: Big Changes Ahead For Connected Vehicles

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

Big Changes Ahead For Connected Vehicles

June 3rd, 2021 - By Ann Steffora Mutschler

Tapping into multiple services, both inside and outside a car, requires a rethinking of everything from architectures to security.

“When you look at the geography of the car, you have to consider how to chop things up,” said Kurt Shuler, vice president of marketing at Arteris IP. “As part of the ECU consolidation discussion, zonal can be one approach such that, for example, ‘the antilock braking system is usually next to this other subsystem, so let’s put those together, and we’ll make that one electronic system that’ll cover all that stuff.’ However, there are still some who say all of this is going to go together, like a centralized architecture where there is a common brain, which makes sense from a functional safety and redundancy standpoint.”

Topics: SoC NoC network-on-chip automotive semiconductor engineering arteris ip interconnects Tier-1 automotive supplier automotive OEMs ECUs service-oriented architectures SOAs zonal architectures Tier 2