Arteris Articles

Semiconductor Engineering: Optimizing NoC-Based Designs

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Semiconductor Engineering article:

Optimizing NoC-Based Designs

May 5th, 2022 - By Paul Graykowski

Further optimization of RTL repartitioning with switching from crossbar interconnects to NoCs.

Semiconductor development is currently in a phase of rapid evolution driven by the combination of new technologies and methodologies. The technique of combining multiple functions into systems-on-chips (SoCs) is continuing to grow in complexity. Rapid advancement in new technologies for market segments like data centers, robotics, ADAS and artificial intelligence/machine learning (AI/ML) are resulting in a new breed of SoCs. These fields demand designs that are maximized for both power and performance efficiency. Designers are finding that networks-on-chip (NoCs) provide the enabling technology to meet this demand and are accelerating the move away from crossbar interconnect technology.

Learn more about Arteris IP Deployment Technology Products .

 

Topics: network-on-chip timing closure ADAS semiconductor engineering latency bandwidth SoCs congestion logic RTL data centers AI/ML NoCs floorplan Arteris IP (AIP) Paul Graykowski partitioning physical design crossbar interconnect robotics

Semiconductor Engineering: Where Do Memory Maps Come From?

Guillaume Boillet, Senior Director of Product Management at Arteris IP authored this Semiconductor Engineering article:

Where Do Memory Maps Come From?

March 3rd, 2022 - By Guillaume Boillet

Ensuring software can accurately address hardware.


A memory map is the bridge between a system-on-chip (SoC) and the firmware and software that is executed on it. Engineers may assume the map automatically appears, but the reality is much more involved. The union of hardware (HW) and software (SW) demands both planning and compromise. The outcome of this merger will not be fully realized until the magical day when the system comes to life.

To learn more about SoC and Hardware/Software Interface (HSI) Development, please download this datasheet:  SoC & Hardware / Software Interface (HSI) Development Datasheet 

 

Topics: software network-on-chip power time to market semiconductor engineering arteris ip hardware SoCs EDA Guillaume Boillet NoCs Arteris IP (AIP) HSI addresses embedded firmware memory map

Design & Reuse: Traceability for Embedded Systems

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Design & Reuse article:

Traceability for Embedded Systems

February 3rd, 2022 - By Paul Graykowski

Maintaining connection between requirements and implementation is where traceability for embedded systems can show value. 

 

In an embedded system, the hardware/software interface (HSI) is a representation of requirements between hardware and software development teams. This description elaborates a huge wealth of detail in memory and IP register offsets, bitfields and detailed behavior specifications. In this representation, at least some aspects must be met precisely. This expectation is especially important because many designs must work with legacy software, not only to minimize development time but also to preserve reliability. A new device replacing one from a different vendor must often mirror all or most of the original HSI. In this context, capturing those requirements and using traceability to track compliance through development becomes a clear advantage.

To learn more about traceability and Arteris Harmony Trace, please download this technical paper: https://www.arteris.com/download-reinventing-traceability-arteris-harmony-trace-paper

Topics: network-on-chip arteris ip verification SoCs RTL UVM compliance EDA traceability NoCs Arteris IP (AIP) validation Arteris Harmony Trace Paul Graykowski Design&Reuse HSI

Semiconductor Engineering: Verification Signoff Beyond Coverage

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Semiconductor Engineering article:

Verification Signoff Beyond Coverage

February 3rd, 2022 - By Paul Graykowski

Ensuring implementation and verification match the customer's requirements.


A common design view of verification signoff is to start with a comprehensive verification plan, covering every requirement defined among specifications and use-cases, the architectural definition, and any other relevant documents. Tests are then developed to cover every feature of the verification plan. Those tests are run and debugged, and identified issues are addressed within the design. This process iterates until the agreed level of coverage is met. Functional coverage is the metric by which this process is gauged, and it works well within its scope. The major electronic design automation (EDA) vendors have tools to run simulations, accumulate coverage statistics, and help further advance those metrics. But this is not the whole story in signoff.

To learn more about traceability and Arteris Harmony Trace, please download this technical paper: https://www.arteris.com/download-reinventing-traceability-arteris-harmony-trace-paper

Topics: network-on-chip automotive semiconductor engineering arteris ip verification SoCs compliance EDA traceability NoCs Arteris IP (AIP) validation Arteris Harmony Trace Paul Graykowski