Arteris Articles

Semiconductor Engineering: Data Explosion Pushes Boundaries of IC Interconnects

Benoit de Lescure, CTO at Arteris IP is quoted in this new article in Semiconductor Engineering:

Data Explosion Pushes Boundaries of IC Interconnects

September 22nd, 2021 - By Ann Steffora Mutschler

Design teams rethink the movement of data on-chip, off-chip, and between chips in a package.


“As chips become extremely large, the interconnect is touching all of the IP blocks in the chip. Benoit de Lescure, CTO at Arteris IP. “In this way, the interconnect is growing like the chip. Other components are not. A PCI controller will stay a PCI controller, but the interconnect size grows along with the size of the chip ,so there are scalability issues, especially because designing a good interconnect requires an understanding of how it will be implemented physically. How will it connect all those components on the chip? What amount of free space on the die will be left for the interconnect to use? What switch topology are you going to implement so that the physical aspects are easier later on? As the size of the problem grows bigger, it becomes significantly more difficult to come up with good interconnect decisions.”

Topics: Interconnect autonomous driving semiconductor engineering arteris ip Benoit de Lescure SoCs kurt shuler PHY scalability floorplan PCI controller switch topology D2D digital controller

Semiconductor Engineering: Choosing Between CCIX and CXL

Kurt Shuler, vice president of marketing at Arteris IP participates in this Experts at the Table, Part 2 with Ed Sperling in this new Semiconductor Engineering article:

Choosing Between CCIX and CXL

May 19th, 2020 - By Ed Sperling

Experts at the Table, Part 2: What's right for one design may not be right for the next. Here's why.
 
Kurt Shuler, vice president of marketing at Arteris IP said, "When CCIX first came out, there was a lot of discussion about doing larger-scale, symmetric cache-coherent systems. But as you add in die or separate chips, and you have to increase memories and caches — and data for what’s going on in the different die, and locally storing that — there’s an architectural line where it doesn’t make much sense anymore. Are you actually losing more than you’re gaining? It’s really, really hard for architects to figure out where that hump is. Even if you have 20 years of experience as a cache-coherent architect, you can’t figure this out anymore in your head or by using Excel. That doesn’t work with CCIX and CXL".
 
To learn more, please click here for the Tech Talk CXL vs. CCIX video: https://www.arteris.com/blog/semiconductor-engineering-cxl-vs.-ccix-video 
 
Topics: SoC automotive CCIX NoC technology semiconductor engineering ADAS systems tech talk video kurt shuler noc interconnect CXL IP market asymmetric PHY cache coherent