Arteris Articles

Semiconductor Engineering: Is Hardware-Assisted Verification Avoidable?

Khaled Labib, Vice President of Engineering at Arteris IP is quoted in this new article in Semiconductor Engineering:

Is Hardware-Assisted Verification Avoidable?

October 28th, 2020 - By Brian Bailey

Simulation is no longer up to the task of system-level verification, but making the switch to hardware-assisted verification can lead to some surprises if you do not fully plan ahead.

Bringing hardware-assisted verification in for the first time is not easy. “For a small company, emulation systems are expensive,” says Arteris’ Labib. “The ones with more advanced features run you about a million dollars for an average starting configuration. If you want to start lower than that, you’re going to have to either give up on features or go with a smaller commercial configuration. But this has become critical to our business, and even as a small company we had to find the necessary budget to buy emulation.”

Topics: SoC NoC semiconductor engineering interconnects emulation noc interconnect IP market cloud khaled labib testbench configurable IP solution regression