Arteris Articles

SemiWiki: The Zen of Auto Safety - a Path to Enlightenment

Kurt Shuler, VP of Marketing and Stefano Lorenzini, Functional Safety Manager at Arteris IP, share stories with Bernard Murphy (SemiWiki) to help you chill. Safety is critical, but that’s doesn't mean you have to panic. 

The Zen of Auto-Safety - a Path to Enlightenment

July 7, 2021 - Bernard Murphy

Safety is a complex topic, but we’re busy. We take the course, get the certificate. Check, along with a million other things we need to do. But maybe it’s not quite that simple. I talked recently with Kurt Shuler (VP of marketing) and Stefano Lorenzini (functional safety manager) at Arteris IP and concluded that finding enlightenment in safety is more of a journey than a destination. I’m going to share with you a few stories they told me which highlight this journey. Because journeys / stories are my favorite way to share an idea.
Topics: SoC NoC network-on-chip semiconductor automotive arteris ip semiwiki functional safety manager RTL FMEDA noc interconnect hybrid AI SoCs Tier 1s AI/ML AoU assumptions of use

Semiconductor Engineering: New Design Approaches For Automotive

Kurt Shuler, VP of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

New Design Approaches For Automotive

July 1st, 2021 - By Ann Steffora Mutschler

OEMs steer toward executable specs using model-based systems engineering.


“If you’re creating an anti-lock braking system or a windshield washer or something like that, it’s relatively simple and you don’t have to spend much time with these tools to be able to come up with that model,” said Kurt Shuler, vice president of marketing at Arteris IP. “But once you get to something really complex like a system on chip — just like with creating SystemC models or the like — you could spend more time than you would on the RTL, or on writing the specs for the RTL, the requirements and use cases for the specs for the RTL, or a SysML model.”

Topics: SoC NoC ISO 26262 ArterisIP SystemC semiconductor engineering arteris ip RTL kurt shuler SoC assembly SysML MBSE

SemiWiki: IP-XACT Resurgence, Design Enterprise Catching Up

Isabelle Geday, VP & GM of the new IP Deployment Division at Arteris IP, gives Bernard Murphy (SemiWiki) insight into some motivations driving companies to switch to IP-XACT.

IP-XACT Resurgence, Design Enterprise Catching Up

June 3, 2021 - Bernard Murphy

This standard has been around in one form or another for over ten years and was then arguably ahead of its time. RTL designers were confused: ‘We already have RTL. Why do we need something else?’ I also didn’t get it. Still, the standard plugged ahead among the faithful and found traction among IP vendors. Particularly as a common format to distribute non-RTL data, like register maps. But a lot has been changing in the meantime. Faster moving competitors. More horizontal and vertical dependencies. Mergers and acquisitions. Chinese technology growth and competition. To adapt, some top-tier organizations have already fully embraced IP-XACT, others are now racing to catch up. Why? Rather than making a dry technical case, I’ll share a few real examples (no names).
Topics: SoC NoC network-on-chip semiconductor arteris ip semiwiki ip-xact RTL noc interconnect AI SoCs Isabelle Geday AI/ML IPD

Semiconductor Engineering: Power Optimization: What's Next?

Guillaume Boillet, Director of Product Management at Arteris IP is quoted in this new article in Semiconductor Engineering:

Power Optimization: What's Next!

May 17th, 2021 - By Brian Bailey

Clock gating and power gating were a good start, but there is much more that can and should be done to minimize power.

“The efforts in terms of methodology, compute resources and engineering talent to deploy system-level techniques are definitely non-negligible,” says Guillaume Boillet, director of product management for Arteris IP. “Only the most advanced and power-savvy design teams invest in those.”

Topics: SoC NoC network-on-chip dynamic power machine learning semiconductor engineering arteris ip interconnects RTL Guillaume Boillet clock-gating macro-level