Arteris Articles

Semiconductor Engineering: Automotive AI Hardware: A New Breed

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article in Semiconductor Engineering:

Automotive AI Hardware: A New Breed

June 3rd, 2021 - By Kurt Shuler

What sets automotive apart from the conventional wisdom on AI hardware markets.

Arteris IP functional safety manager Stefano Lorenzini recently presented “Automotive Systems-on-Chip (SoCs) with AI/ML and Functional Safety” at the Linley Processor Conference. A main point of the presentation was that conventional wisdom on AI hardware markets is binary. There’s AI in the cloud: Big, power-hungry, general-purpose. And there’s AI at the edge: Small, low power, limited application-specific features. Automotive AI doesn’t really fit into either category. To power ADAS and autonomous driving functions, these chips are extremely application-specific and require more performance than typical edge AI, are low power but not as low as IoT chips at the edge, and must be as low cost as possible. They also add a new angle – low latency because safety demands fast and deterministic response times. Add to all that the functional safety requirements demanded by ISO 26262 – inside the AI structure as much as everywhere else. Bottom line: Automotive AI SoC architectures are unique beasts.

Topics: SoC NoC functional safety network-on-chip automotive ECC The Linley Group ISO 26262 compliance semiconductor engineering arteris ip interconnects kurt shuler AI SoCs AI/ML Stefano Lorenzini heterogeneous socs ASIL

Semiconductor Engineering: Power Optimization: What's Next?

Guillaume Boillet, Director of Product Management at Arteris IP is quoted in this new article in Semiconductor Engineering:

Power Optimization: What's Next!

May 17th, 2021 - By Brian Bailey

Clock gating and power gating were a good start, but there is much more that can and should be done to minimize power.

“The efforts in terms of methodology, compute resources and engineering talent to deploy system-level techniques are definitely non-negligible,” says Guillaume Boillet, director of product management for Arteris IP. “Only the most advanced and power-savvy design teams invest in those.”

Topics: SoC NoC network-on-chip dynamic power machine learning semiconductor engineering arteris ip interconnects RTL Guillaume Boillet clock-gating macro-level

Semiconductor Engineering: HBM Takes On A Much Bigger Role

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new article in Semiconductor Engineering:

HBM Takes On A Much Bigger Role

May 13th, 2021 - By Brian Bailey

High-bandwidth memory may be a significant gateway technology that allows the industry to make a controlled transition to true 3D design and assembly.

“The benefit of HBM is really its high bandwidth,” says Michael Frank, fellow and system architect at Arteris IP. “If you have a working data set that fits, it’s fine. To consume that much bandwidth, you are likely to use a decent amount of silicon area to process it. But HBM does not providing the low latency that you get from SRAMs. You have to look at your application. What is your algorithm? In many systems, you sequentially process a lot of data, mostly with the same kind of processing scheme. It’s like SIMD or streaming. Machine learning is typically something like this, where you have large data sets and weights. But HBM is still limited in capacity, and the price is relatively high.”

Topics: SoC NoC network-on-chip machine learning semiconductor engineering arteris ip interconnects Michael Frank DRAMS SMID

Semiconductor Engineering: IC Security Threat Grows As More Devices Are Connected

Guillaume Boillet, Director of Product Management at Arteris IP is quoted in this new article in Semiconductor Engineering:

IC Security Threat Grows As More Devices Are Connected 

May 6th, 2021 - By Ann Steffora Mutschler

Awareness increases, but so does the complexity of systems and the potential attack surface.

 “We would expect this industry to be adopting cloud-based software-as-a-service massively, but the reality is different,” said Guillaume Boillet, director of product management at Arteris IP. “The design environment itself is almost always in a customer-owned data center. There has been some push to leverage the benefits of the cloud, and of course it’s very appealing because now you can scale your data centers. But I don’t have an example where, all of a sudden, you’ve got a need for more computing power and you would rather rely on the cloud than build a rack. This is not happening for multiple reasons. One, people are very protective of their IP, of what they’re doing, so it’s been an hindrance for us in terms of support, etc. Also, moving to the SaaS model requires a total rethink of the licensing, because it’s a totally different monetization scheme. I’ve seen examples where this scenario would have required a lot of work and a lot of revamping of the toolset.”

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip interconnects datacenters security Guillaume Boillet ecosystem security