Arteris Articles

Value chains can be very robust and seemingly unbreakable – until they’re not. One we’ve taken for granted for many years is the chain for electronics systems in cars. The auto OEM, e.g. Toyota, gets electronics module from a Tier-1 supplier such as Denso. They, in turn, build their modules using chips from a semiconductor chip maker such as Renesas, who produces their chips using pre-packaged functions from IP providers like Arm. Toyota could do the whole thing themselves, but it’s very expensive to set-up and maintain all of that infrastructure. Specialization makes it all more practical. Everyone makes money doing their bit well and cost-effectively and being able to sell to multiple customers (Toyota, GM, BMW, etc.). However, that cash flow can be upended when disruptive innovations are thrown into the supply chain, in this case, a lot more intelligence and autonomy. I talked to Kurt Shuler (VP Marketing at Arteris IP) to get his view. Kurt is an IP supplier and has a unique viewpoint because he works with semis, Tier-1s and OEMs, with standard designs as well as newer AI-based designs. He’s also an active member of the ISO 26262 committee.

There’s a lot of debate about how and when we are going to emerge from the worldwide economic downturn triggered by the pandemic. Everyone agrees we will emerge. This isn’t humanity’s first pandemic, nor will it be our last. But do we come out quickly or slowly? And what does the economy look like on the other side, particularly for the domain we care about – electronic design?

The nexus of complexity in SoC design these days has to be in automotive ADAS devices. Arteris IP highlighted this in the Linley Processor Conference recently where they talked about an ADAS chip that Toshiba had built. This has multiple vision and AI accelerators, both DSP and DNN-based. It is clearly aiming for ISO 26262 ASIL D certification since the design separates a safety island from the processing island, pretty much the only way you can get to ASIL D in a heterogenous mix of ASIL-level on-chip subsystems. Equally clear, it’s aiming to run at low power – around 2.7W for the processing island (the bulk of the functionality). It’s all very well to be smart but when you have dozens of smart components scattered around the car, that adds up to a lot of power consumption. The car isn’t going to be very smart if it runs its battery flat.

Last-level cache seemed to me like one of those, yeah I get it, but sort of obscure technical corners that only uber-geek cache specialists would care about. Then I stumbled on an AnandTech review on the iPhone 11 Pro and Max and started to understand that this contributes to more than just engineering satisfaction.

For more information, please download this paper: https://www.arteris.com/download-technical-paper-codacache-helping-to-break-the-memory-wall