Kurt Shuler, vice president of marketing at Arteris IP comments, he has seen that development is quickly moving in the direction of optimization with a lot of custom ASIC activity this Semiconductor Engineering article:
Uses, Limits and Questions for FPGAs and Autos
February 6th, 2020 - By Ann Steffora Mutschler
“Some companies are getting beyond the bounds of what can be done even in single die, looking at multidie solutions, but everything’s around optimization for power, bandwidth, latency, and functional safety,” Shuler said. “When you go to FPGA, the biggest issue is probably on the power side. Compared to a similar set of logic in ASIC versus doing an FPGA, you’ve got to basically turn on and off more transistors. That’s the underlying technical issue.
To learn more, please download this Technical Paper on "Re-Architecting SoCs for the AI Era", please go here; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era