Benny Winefeld, solutions architect at Arteris IP, adds additional commentary to this Semiconductor Engineering article:
More Nodes, New Problems
April 26th, 2018 - By Ann Steffora Mutschler
by Madelyn Miller, on Mon, Apr 30, 2018 @ 12:02 PM
Benny Winefeld, solutions architect at Arteris IP, adds additional commentary to this Semiconductor Engineering article:
April 26th, 2018 - By Ann Steffora Mutschler
by Kurt Shuler, on Wed, Apr 08, 2015 @ 12:11 PM
We announced FlexNoC Version 3 today!
Our primary engineering goal with this totally new technology release was to increase the productivity of our SoC designer users.
As the size and complexity of our user’s SoC designs increased over the years, it had become increasingly difficult to visualize and optimize a huge design in a single GUI window. In addition, we saw the need to make the FlexNoC user interface adapt to whatever task the user is performing, rather than provide the same access to the many options within FlexNoC.
Under the hood, we increased the performance of all aspects of the product, not just user interface response but also performance modeling and exploration.
Here are the top 3 features in the new FlexNoC Version 3:
NEXT STEPS:
Current customers can upgrade from the current version of FlexNoC to FlexNoC Version 3. Just contact your Arteris sales manager.
For prospective customers, please contact me and we'll get you started!
For more details, please read our press announcement below.
by Kurt Shuler, on Tue, Mar 03, 2015 @ 01:59 PM
As system on chip designs grow more complex, it becomes more and more difficult for chip companies to optimize the work of their distributed design teams. While each separate team has an area of expertise and sets their focus on a particular aspect of the SoC, the hard part comes in integrating these individual design efforts together. When something goes wrong and it doesn’t work, the company’s critical time to market advantage starts to slip.
by Kurt Shuler, on Mon, Feb 02, 2015 @ 04:40 PM
Author's note: This article was originally published in Design & Reuse where it has been read by nearly 2,000 engineers and shared by over 100 people.
Let’s face it, Moore’s Law has been the free lunch program of the semiconductor industry. And now that Moore’s Law is dead, how will SoC designers continue to survive?
News and original writing about on-chip interconnects, on-chip communications and the semiconductor intellectual property ("semi IP") industry.
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