Arteris Articles

Benny Winefeld, solutions architect at Arteris IP, adds additional commentary to this Semiconductor Engineering article:

More Nodes, New Problems

April 26th, 2018 - By Ann Steffora Mutschler

We announced FlexNoC Version 3 today!

Our primary engineering goal with this totally new technology release was to increase the productivity of our SoC designer users.

As the size and complexity of our user’s SoC designs increased over the years, it had become increasingly difficult to visualize and optimize a huge design in a single GUI window. In addition, we saw the need to make the FlexNoC user interface adapt to whatever task the user is performing, rather than provide the same access to the many options within FlexNoC.

Under the hood, we increased the performance of all aspects of the product, not just user interface response but also performance modeling and exploration.

Here are the top 3 features in the new FlexNoC Version 3:

1. Switch-based topology editor – It is now easier to create, characterize and modify large designs while keeping access to the entire SoC topology available within a single view.
2. Topic- and activity-based user interface – Years of customer feedback and human factors research have resulted in a streamlined interface that makes it easier for SoC architects and designers to perform complex and repetitive tasks.
3. NoC composition enhancements – Users can more easily break large interconnect designs into smaller modules for implementation by different sub-teams, and can quickly combine separate designs or modules into a single interconnect instance for integration.

NEXT STEPS:

Current customers can upgrade from the current version of FlexNoC to FlexNoC Version 3. Just contact your Arteris sales manager.

For prospective customers, please contact me and we'll get you started!

For more details, please read our press announcement below.

Specialized teams find new ways to stitch individual efforts into the SoC fabric.

As system on chip designs grow more complex, it becomes more and more difficult for chip companies to optimize the work of their distributed design teams. While each separate team has an area of expertise and sets their focus on a particular aspect of the SoC, the hard part comes in integrating these individual design efforts together. When something goes wrong and it doesn’t work, the company’s critical time to market advantage starts to slip.

Author's note: This article was originally published in Design & Reuse where it has been read by nearly 2,000 engineers and shared by over 100 people.

As the "Free Lunch" Era Closes, Chip Designers Grow in Value by Providing Innovative Ways to Increase Performance and Cut Power Consumption

Let’s face it, Moore’s Law has been the free lunch program of the semiconductor industry. And now that Moore’s Law is dead, how will SoC designers continue to survive?