Arteris Articles

Semiconductor Engineering: More NoC Wisdom

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article in Semiconductor Engineering:

More NoC Wisdom

October 7th, 2021 - By Kurt Shuler

Managing expectations for disruptive technologies.


A common experience for anyone promoting a disruptive technology is that prospective customers understand that what is being offered is different. Still, without a familiar reference to compare, they extrapolate expectations unreliably. Thinking of a switch to network-on-chip (NoC)? Here is wisdom for review.


Topics: network-on-chip Ncore semiconductor engineering arteris ip SoCs kurt shuler PPA chip design automotive SOCs NoCs NoC IP FIFOs AI training architectures

Semiconductor Engineering: NoC Experiences From The Trenches

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article in Semiconductor Engineering:

NoC Experiences From The Trenches

September 28th, 2021 - By Kurt Shuler

When evaluating a new technology, don't aim for a simple 1-to-1 replacement.


Network-on-chip (NoC) interconnect as an alternative to traditional crossbars is already well-proven, but there are still plenty of design teams on the cusp of a transition or who maybe do not yet see a need for a change. As with a switch to any new technology, the first hurdles are often simply misconceptions. When new users first evaluate any new technology, they often make the mistake of attempting a 1-to-1 replacement of their old technology without considering all the new things the new capabilities bring to them.

Read on for some examples I have seen during my years at Arteris IP and check out our customer list, which includes the best-of-the-best in many domains implementing small to large designs.

Topics: Interconnect network-on-chip crossbar automotive FlexNoC semiconductor engineering arteris ip CPUs SoCs RTL kurt shuler chip design NoCs AI designs floorplanning

Semiconductor Engineering: Software-Hardware Co-Design Becomes Real

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new article in Semiconductor Engineering:

Software-Hardware Co-Design Becomes Real

September 27th, 2021 - By Brian Bailey

Automatic mapping of software onto existing hardware, or using software to drive hardware design, are highly desired but very difficult.


“Hardware/software co-design has been happening for quite a while,” says Michael Frank, fellow and system architect at Arteris IP. “People have been trying to estimate the behavior of the platform and evaluation its performance using real software for quite a while. The industry has been building better simulators, such as Gem5, and Qemu. This has extended into systems where accelerators have been included, where you build models of accelerators and offload your CPUs by running parts of the code on the accelerator."

Topics: Interconnect automotive semiconductor engineering arteris ip CPUs SoCs chip design AI/ML Michael Frank Gem5

Semiconductor Engineering: Data Explosion Pushes Boundaries of IC Interconnects

Benoit de Lescure, CTO at Arteris IP is quoted in this new article in Semiconductor Engineering:

Data Explosion Pushes Boundaries of IC Interconnects

September 22nd, 2021 - By Ann Steffora Mutschler

Design teams rethink the movement of data on-chip, off-chip, and between chips in a package.


“As chips become extremely large, the interconnect is touching all of the IP blocks in the chip. Benoit de Lescure, CTO at Arteris IP. “In this way, the interconnect is growing like the chip. Other components are not. A PCI controller will stay a PCI controller, but the interconnect size grows along with the size of the chip ,so there are scalability issues, especially because designing a good interconnect requires an understanding of how it will be implemented physically. How will it connect all those components on the chip? What amount of free space on the die will be left for the interconnect to use? What switch topology are you going to implement so that the physical aspects are easier later on? As the size of the problem grows bigger, it becomes significantly more difficult to come up with good interconnect decisions.”

Topics: Interconnect autonomous driving semiconductor engineering arteris ip Benoit de Lescure SoCs kurt shuler PHY scalability floorplan PCI controller switch topology D2D digital controller