Arteris Articles

Semiconductor Engineering: Learning ISO 26262 - 2nd Edition

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article on the interpretation of ISO 26262 in today's Semiconductor Engineering blog:

Learning ISO 26262 -2nd Edition 

December 7th, 2020 - By Kurt Shuler

Interpreting the functional safety standard isn't as simple as just looking at the document.

Ambiguity is a feature, not a bug!

Why? Partly ambiguity. Because what I think is clear, you may not think is clear. And some of this ambiguity is intentional: This is a voluntary (thought widely followed) standard, aiming to preserve flexibility for innovation and differentiation. The committees don't want to be too prescriptive, which inevitably leads to some ambiguity.

Topics: SoC NoC functional safety ISO 26262 automotive semiconductor engineering Soft IP FMEA kurt shuler OEMs FMEDA noc interconnect IP market Part 11 tailoring safety element standards SEooC

Arteris IP Awarded 1st Place for Technical Paper at Synopsys Users Group (SNUG) Silicon Valley 2019

Benny Winefeld, Solutions Architect at Arteris IP, Awarded 1st Place Best Paper Award at SNUG Silicon Valley 2019 

Arteris IP presented this technical paper, "Using Machine Learning for Characterization of NoC Components", on March 20, 2019.

Benny Winefeld, Solutions Architect at Arteris IP, accepted the 1st Place Best Paper Award from the SNUG Technical Committee during SNUG Silicon Valley. There were 29 papers that competed for the best paper award.

In the photo above, Benny receives the award from the SNUG committee, from left to right: Ken Nelson, VP Field Support Operations; Benny Winefeld, Solutions Architect, Arteris IP; Tony Todesco, SNUG SV Technical Chair, AMD; and Deirdre Hanford, Co-GM, Synopsys.

Topics: Synopsys NoC machine learning artificial intelligence Soft IP noc interconnect SNUG

Arteris IP at DATE 2019

Arteris IP at DATE 2019 

Location: Firenze Fiera, Florence, Italy
3.1 Executive Session 2: Panel
Date:
Tuesday, 26 March 2019
Time: 14:30 - 16:00
Location: Room 1

Arteris IP's CEO, K. Charles Janac joins this Executive Panel Session, "Semiconductor IP, Surfing the Next Big Wave"

Topics: FPGA semiconductor Soft IP SoCs noc interconnect hard ip

Arteris IP at Synopsys Users Group Silicon Valley 2019


Arteris IP at SNUG Silicon Valley 2019 

Location: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA  
Track: Artificial Intelligence - Wednesday, 20 March, 3:45 pm - 4:30 pm

Arteris IP is presenting this paper, "Using Machine Learning for Characterization of NoC Components"

Topics: NoC semiconductor FlexNoC Soft IP SoCs RTL noc interconnect ML PPA