Arteris Articles

Arteris IP Awarded 1st Place for Technical Paper at Synopsys Users Group (SNUG) Silicon Valley 2019

by Madelyn Miller, on Thu, Apr 04, 2019 @ 10:36 AM

Benny Winefeld, Solutions Architect at Arteris IP, Awarded 1st Place Best Paper Award at SNUG Silicon Valley 2019

Arteris IP presented this technical paper, "Using Machine Learning for Characterization of NoC Components", on March 20, 2019.

Benny Winefeld, Solutions Architect at Arteris IP, accepted the 1st Place Best Paper Award from the SNUG Technical Committee during SNUG Silicon Valley. There were 29 papers that competed for the best paper award.

In the photo above, Benny receives the award from the SNUG committee, from left to right: Ken Nelson, VP Field Support Operations; Benny Winefeld, Solutions Architect, Arteris IP; Tony Todesco, SNUG SV Technical Chair, AMD; and Deirdre Hanford, Co-GM, Synopsys.

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Topics: Synopsys NoC machine learning artificial intelligence Soft IP noc interconnect SNUG

Arteris and Synopsys Webinar Held on Wednesday, 26 September

by Madelyn Miller, on Mon, Sep 17, 2018 @ 05:54 PM

synopsys_color_600px Holger Keding (Synopsys' Solutions Architect), Rocco Jonack (Arteris' Senior Solutions Architect) and Malte Doerper (Synopsys' Product Marketing) will be jointly hosting this webinar,
"Optimization of Cache Coherent Interconnects for Artificial Intelligence SoCs",
on Wednesday, 26 September, at 10 am Pacific time.

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Topics: Synopsys cache coherent interconnect artificial intelligence SoCs webinar architect

IEEE Electronics 360: How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

by Madelyn Miller, on Wed, Aug 08, 2018 @ 09:48 AM

Learn from the experts at Arteris IP in this new White Paper:

How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

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Topics: SoC economics Synopsys functional safety semiconductor automotive ADAS ISO 26262 compliance artificial intelligence arteris ip latency ASIL D interconnects soc designers aerospace aeronautics LED kurt shuler Z01X Austemper

New Synopsys verification solution integrates with Arteris Ncore cache coherent interconnect

by Kurt Shuler, on Tue, May 24, 2016 @ 01:00 PM

Synopsys announced their new cache coherent subsystem verification solution which integrates with Arteris Ncore: Synopsys Delivers Industry's First Cache Coherent Subsystem Verification Solution for Arteris Ncore Interconnect.

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Topics: Synopsys hardware verification Ncore

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Arteris IP Awarded 1st Place for Technical Paper at Synopsys Users Group (SNUG) Silicon Valley 2019

Benny Winefeld, Solutions Architect at Arteris IP, Awarded 1st Place Best Paper Award at SNUG Silicon Valley 2019

Arteris and Synopsys Webinar Held on Wednesday, 26 September

IEEE Electronics 360: How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

New Synopsys verification solution integrates with Arteris Ncore cache coherent interconnect