Arteris Articles

Semiconductor Engineering: Choosing Between CCIX and CXL

Kurt Shuler, vice president of marketing at Arteris IP participates in this Experts at the Table, Part 2 with Ed Sperling in this new Semiconductor Engineering article:

Choosing Between CCIX and CXL

May 19th, 2020 - By Ed Sperling

Experts at the Table, Part 2: What's right for one design may not be right for the next. Here's why.
 
Kurt Shuler, vice president of marketing at Arteris IP said, "When CCIX first came out, there was a lot of discussion about doing larger-scale, symmetric cache-coherent systems. But as you add in die or separate chips, and you have to increase memories and caches — and data for what’s going on in the different die, and locally storing that — there’s an architectural line where it doesn’t make much sense anymore. Are you actually losing more than you’re gaining? It’s really, really hard for architects to figure out where that hump is. Even if you have 20 years of experience as a cache-coherent architect, you can’t figure this out anymore in your head or by using Excel. That doesn’t work with CCIX and CXL".
 
To learn more, please click here for the Tech Talk CXL vs. CCIX video: https://www.arteris.com/blog/semiconductor-engineering-cxl-vs.-ccix-video 
 
Topics: SoC automotive CCIX NoC technology semiconductor engineering ADAS systems tech talk video kurt shuler noc interconnect CXL IP market asymmetric PHY cache coherent

Semiconductor Engineering: Which Chip Interconnect Protocol is Better?

Kurt Shuler, vice president of marketing at Arteris IP participates in this Experts at the Table with Ed Sperling in this new Semiconductor Engineering article:

Which Chip Interconnect Protocol is Better?

May 11th, 2020 - By Ed Sperling

Experts at the Table: CXL and CCIX are different but it's not always clear which is the best choice.
 
"Everybody is circling around and trying to figure out what everybody else is doing, said Kurt Shuler, vice president of marketing at Arteris IP. CCIX is a little different. The idea there was that you would have one or more chips and they would all be one cache coherent system. So in the case of CXL, the coherency is all managed on the Xeon side, and that companion chip is always a slave. It’s different with CCIX. So if you do the bi-directional coherency, which is what people are interested in, it’s one big cache-coherent system".
 
To learn more, please click here for the Tech Talk CXL vs. CCIX video: https://www.arteris.com/blog/semiconductor-engineering-cxl-vs.-ccix-video 
 
Topics: SoC automotive CCIX NoC technology semiconductor engineering tech talk video kurt shuler data centers noc interconnect CXL IP market

Semiconductor Engineering: Who Owns A Car's Chip Architecture Video

Tech Talk Video: Who Owns a Car's Chip Architecture 

May 5th, 2020 - By Ed Sperling

Kurt Shuler, vice president of marketing at Arteris IP, examines the competitive battle brewing between OEMs and Tier 1s over who owns the architecture of the electronic systems and the underlying chip hardware. This has become a growing point of contention as both struggle for differentiation in a market where increasingly autonomous vehicles will all behave the same way. That, in turn, has significant implications for customization and standards, as well as the hiring of chip expertise inside of these companies as companies race toward fully autonomous driving.

Topics: network-on-chip semiconductor low power ADAS tech talk video on-chip memory data centers automotive chips semiengineering

Semiconductor Engineering: Last-Level Cache Video

Tech Talk Video: Last-Level Cache 

April 6th, 2020 - By Ed Sperling

Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources.

Topics: network-on-chip semiconductor CodaCache tech talk video on-chip memory data centers memory hierarchy semiengineering