Arteris Articles

Semiconductor Engineering: Optimizing NoC-Based Designs

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Semiconductor Engineering article:

Optimizing NoC-Based Designs

May 5th, 2022 - By Paul Graykowski

Further optimization of RTL repartitioning with switching from crossbar interconnects to NoCs.

Semiconductor development is currently in a phase of rapid evolution driven by the combination of new technologies and methodologies. The technique of combining multiple functions into systems-on-chips (SoCs) is continuing to grow in complexity. Rapid advancement in new technologies for market segments like data centers, robotics, ADAS and artificial intelligence/machine learning (AI/ML) are resulting in a new breed of SoCs. These fields demand designs that are maximized for both power and performance efficiency. Designers are finding that networks-on-chip (NoCs) provide the enabling technology to meet this demand and are accelerating the move away from crossbar interconnect technology.

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Topics: network-on-chip timing closure ADAS semiconductor engineering latency bandwidth SoCs congestion logic RTL data centers AI/ML NoCs floorplan Arteris IP (AIP) Paul Graykowski partitioning physical design crossbar interconnect robotics

The Critical Cost of Routing Congestion

By Jonah Probell, Senior Solutions Architect, Arteris

Topics: SoC SoC economics SoC design routing congestion timing closure

The 3 Evils of Routing Congestion

Much of the talk today in the system on chip (SoC) ASIC business is about how smaller critical dimensions are driving the use of more and more IP blocks on a single SoC. As the number of IP blocks increases, the act of assembling and physically manufacturing the SoC become Herculean. What’s the big deal?

Topics: routing congestion timing closure