Arteris Articles

SemiWiki: An Ah-Ha Moment for Testbench Assembly

Bernard Murphy (SemiWiki) gets an update from Arteris IP.

An Ah-Ha Moment for Testbench Assembly 

February 28, 2022 - Bernard Murphy

Sometimes we miss the forest for the trees, and I’m as guilty as anyone else. When we think testbenches, we rightly turn to UVM because that’s the agreed standard, and everyone has been investing their energy in learning UVM. UVM is fine, so why do we need to talk about anything different? That’s the forest and trees thing. We don’t need to change the way we define testbenches – the behavior and (largely) the top-level structure. But maybe there’s a better way to assemble that top level through a more structured assembly method than through hand-coding or ad-hoc scripting. Still built on UVM at leveraging the standardization benefits of IP-XACT for assembly around VIPs.
 
Topics: SoC NoC network-on-chip semiconductor arteris ip semiwiki ip-xact RTL UVM noc interconnect test bench assembly Arteris IP Harmony Trace Paul Graykowski Jama software SoC verification Magillem UTG UVM Testbench Generator Arteris (AIP)

Design & Reuse: Traceability for Embedded Systems

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Design & Reuse article:

Traceability for Embedded Systems

February 3rd, 2022 - By Paul Graykowski

Maintaining connection between requirements and implementation is where traceability for embedded systems can show value. 

 

In an embedded system, the hardware/software interface (HSI) is a representation of requirements between hardware and software development teams. This description elaborates a huge wealth of detail in memory and IP register offsets, bitfields and detailed behavior specifications. In this representation, at least some aspects must be met precisely. This expectation is especially important because many designs must work with legacy software, not only to minimize development time but also to preserve reliability. A new device replacing one from a different vendor must often mirror all or most of the original HSI. In this context, capturing those requirements and using traceability to track compliance through development becomes a clear advantage.

To learn more about traceability and Arteris Harmony Trace, please download this technical paper: https://www.arteris.com/download-reinventing-traceability-arteris-harmony-trace-paper

Topics: network-on-chip arteris ip verification SoCs RTL UVM compliance EDA traceability NoCs Arteris IP (AIP) validation Arteris Harmony Trace Paul Graykowski Design&Reuse HSI

EDA Cafe: Arteris IP Extends IP-XACT to UVM Testbenches

Vincent Thibaut, Director of IP Deployment Product Strategy at Arteris IP authored this new article for EDA Cafe:

Arteris IP Extends IP-XACT to UVM Testbenches

July 2, 2021 - By Vincent Thibaut


To be clear, the goal here is not to autogenerate the internals of the complex test sequences. However, the IP-XACT platform from Arteris IP does handle register sequences. Instead, view the universal verification methodology (UVM) testbench as part of an assembly of the device under test (DUT), plus many complex VIPs. IP-XACT lends itself nicely to this concept. To be effective, packaging needs several extensions so that configuration can be managed from the IP-XACT level. Testbenches will be challenged to include more and more VIPs as design complexity grows. There are compelling reasons to explore IP-XACT packaging for VIPs.

Topics: SoC NoC arteris ip verification ip-xact UVM ip deployment IPD testbench assembly DUT SoC testbenches vincent thibaut VIPs UVM testbenches

Semiconductor Engineering: Bugs That Kill

Charlie Janac, CEO at Arteris IP, participated in this 'Behind Closed Doors' semiconductor executives dinner at DAC, hosted by Craig Shirley, president and CEO of Oski Technology.

Bugs That Kill

 

August 23rd, 2018 - By Brian Bailey

Topics: semiconductor autonomous vehicles semiconductor engineering arteris ip interconnects oski technology bugs UVM charlie janac