Arteris Articles

Design & Reuse: Traceability for Embedded Systems

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Design & Reuse article:

Traceability for Embedded Systems

February 3rd, 2022 - By Paul Graykowski

Maintaining connection between requirements and implementation is where traceability for embedded systems can show value. 

 

In an embedded system, the hardware/software interface (HSI) is a representation of requirements between hardware and software development teams. This description elaborates a huge wealth of detail in memory and IP register offsets, bitfields and detailed behavior specifications. In this representation, at least some aspects must be met precisely. This expectation is especially important because many designs must work with legacy software, not only to minimize development time but also to preserve reliability. A new device replacing one from a different vendor must often mirror all or most of the original HSI. In this context, capturing those requirements and using traceability to track compliance through development becomes a clear advantage.

To learn more about traceability and Arteris Harmony Trace, please download this technical paper: https://www.arteris.com/download-reinventing-traceability-arteris-harmony-trace-paper

Topics: network-on-chip arteris ip verification SoCs RTL UVM compliance EDA traceability NoCs Arteris IP (AIP) validation Arteris Harmony Trace Paul Graykowski Design&Reuse HSI

Semiconductor Engineering: Verification Signoff Beyond Coverage

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Semiconductor Engineering article:

Verification Signoff Beyond Coverage

February 3rd, 2022 - By Paul Graykowski

Ensuring implementation and verification match the customer's requirements.


A common design view of verification signoff is to start with a comprehensive verification plan, covering every requirement defined among specifications and use-cases, the architectural definition, and any other relevant documents. Tests are then developed to cover every feature of the verification plan. Those tests are run and debugged, and identified issues are addressed within the design. This process iterates until the agreed level of coverage is met. Functional coverage is the metric by which this process is gauged, and it works well within its scope. The major electronic design automation (EDA) vendors have tools to run simulations, accumulate coverage statistics, and help further advance those metrics. But this is not the whole story in signoff.

To learn more about traceability and Arteris Harmony Trace, please download this technical paper: https://www.arteris.com/download-reinventing-traceability-arteris-harmony-trace-paper

Topics: network-on-chip automotive semiconductor engineering arteris ip verification SoCs compliance EDA traceability NoCs Arteris IP (AIP) validation Arteris Harmony Trace Paul Graykowski

Semiconductor Engineering: Traceability, Unfamiliar But Critical

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Semiconductor Engineering article:

Traceability, Unfamiliar But Critical

January 6th, 2022 - By Paul Graykowski

Automatically maintain traceability from requirements to implementation and verification.


Many understand that traceability is a popular concept. Still, understanding traceability in detail is more challenging, especially in how it connects to familiar objectives in the semiconductor design space.

To learn more about traceability and Arteris Harmony Trace, please download this technical paper: https://www.arteris.com/download-reinventing-traceability-arteris-harmony-trace-paper

Topics: network-on-chip automotive semiconductor engineering arteris ip verification SoCs EDA NoCs Arteris IP (AIP) requirements validation Arteris Harmony Trace Jama Connect Accellera Paul Graykowski