Arteris Articles

EDA Cafe: Arteris IP Extends IP-XACT to UVM Testbenches

Vincent Thibaut, Director of IP Deployment Product Strategy at Arteris IP authored this new article for EDA Cafe:

Arteris IP Extends IP-XACT to UVM Testbenches

July 2, 2021 - By Vincent Thibaut

To be clear, the goal here is not to autogenerate the internals of the complex test sequences. However, the IP-XACT platform from Arteris IP does handle register sequences. Instead, view the universal verification methodology (UVM) testbench as part of an assembly of the device under test (DUT), plus many complex VIPs. IP-XACT lends itself nicely to this concept. To be effective, packaging needs several extensions so that configuration can be managed from the IP-XACT level. Testbenches will be challenged to include more and more VIPs as design complexity grows. There are compelling reasons to explore IP-XACT packaging for VIPs.

Topics: SoC NoC arteris ip verification ip-xact UVM ip deployment IPD testbench assembly DUT SoC testbenches vincent thibaut VIPs UVM testbenches

Semiconductor Engineering: Shifting Toward Data-Driven Chip Architectures

K. Charles Janac, CEO at Arteris IP is quoted in this new article in Semiconductor Engineering:

Shifting Toward Data-Driven Chip Architectures

June 16th, 2021 - By Ed Sperling and Ann Steffora Mutschler

Rethinking how to improve performance and lower power in semiconductors.

“There are dynamic routing opportunities at runtime,” said K. Charles Janac, chairman and CEO of Arteris IP. “We’ve always resisted runtime dynamic routing because there are issues with verification. If you have billions of transactions, the verification is much simpler if you’re forcing the traffic to go onto a single connection every time. But there are opportunities for easing that in the future and have the NoC essentially be able to reroute traffic dynamically based on some sort of routing controller, which in turn is controlled by some global software."

Topics: SoC NoC network-on-chip automotive machine learning semiconductor engineering arteris ip verification K. Charles Janac interconnects datacenters

Semiconductor Engineering: Taming Non-Predictable Systems

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this Semiconductor Engineering blog:

Taming Non-Predictable Systems

January 28th, 2021 - By Brian Bailey

The non-predictable nature of most systems is not inherently bad, so long as it is understood and bounded — but that’s becoming a bigger challenge.

“Real-time is a ‘stretchable’ term,” says Michael Frank, fellow and system architect at Arteris IP. “In general, it implies that a certain action is completed within a bounded time, with 100 % probability, as opposed to engineering schedules. For most real-time systems, the definition is not that strict. Some systems are fine if the average is within a certain window that meets the requirement, such as for video decoding. Other cases may look to see if the deadline will only be missed with a certain low random probability. Those systems may replace a missing result by a prediction/interpolation, such as dropped audio samples.”

Topics: SoC NoC network-on-chip semiconductor engineering AI verification real-time systems Michael Frank

Semiconductor Engineering: Productivity Keeping Pace With Complexity

Benoit de Lescure, CTO at Arteris IP is quoted in this new article in Semiconductor Engineering:

Productivity Keeping Pace With Complexity

September 25th, 2020 - By Brian Bailey

Without productivity gains, design size and complexity would face huge headwinds. Those gains come from a diverse set of improvements.

Nobody doubts the power of reuse. Intellectual Property blocks are either built into a library for those inside of large companies, or if you’re a small company, you go outside and you buy it,” says Benoit de Lescure, CTO for Arteris IP. “Complexity is managed through a divide and conquer strategy. Companies are also using larger macro functions that you stitch together with the same amount of people. Today, you can buy a multiple CPU block, with Level 3 cache, and complex cache coherent interconnect. These have been designed to be easy to configure, and so you can create a very large CPU complex with 8 or 16 CPUs, and that becomes the macro functions you’re integrating.”

Topics: SoC NoC automotive cache coherent interconnect semiconductor engineering soc architecture CPUs Benoit de Lescure verification noc interconnect ML/AI IP market