Implementing Machine Learning and Neural Network Chip Architectures

Using Network-on-Chip Interconnect IP

ArterisIP - implementing machine learning and neural network chip architectures-4001x2251-borderDownload this 17-slide presentation titled, "Implementing Machine Learning and Neural Network Chip Architectures," presented by Arteris IP CTO Ty Garibay.


  • Types processing elements for neural net acceleration
  • Current state-of-the-art AI SoC architectures
  • Influence of interconnect and memory architectures on AI data flow




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