Automating the generation of scalable and reusable FMEDA in complex Systems-on-Chip (SoCs)

IQPC Application of ISO 26262 Conference Presentation

Pages from Arteris_IP_FMEDA_Automation_1.1 - Public.pdf-1Download this 14-slide presentation titled, "Automating the generation of scalable and reusable FMEDA in complex Systems-on-Chip (SoCs)" presented by Stefano Lorenzini, Functional Safety Manager of Arteris IP, at IQPC Application of ISO 26262 Conference 2022.

Failure modes, effects, and diagnostic analysis (FMEDA) for sophisticated chips with hundreds of IP blocks is fraught with complexity and opportunities for systematic errors. The author describes an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics at a level that scales with the size and complexity of an SoC and enables reuse for the creation of SoC platform derivative chips, which is common in our industry. Using this bottoms-up approach allows for increased automation and less FMEDA rework as the chip’s architecture is refined and changed during development. Linkages to traceability is also discussed.

   

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