Using machine learning for characterizations of NoC components
Synopsys Users Group (SNUG), March 2019, SNUG Silicon Valley.
Download this first place award winning conference paper titled, "Using machine learning for characterizations of NoC components”, authored by Arteris IP's Benny Winefeld, Solutions Architect, at the Synopsys Users Group (SNUG), March 2019, SNUG Silicon Valley.
Includes:
- Conference paper, 15 pages
- Abstract: Modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters. PPA (performance/power/area) estimates for these components are highly desirable during early design phases – long before NoC gate level netlist is synthesized. At this stage a NoC component is a soft module, described by a set of architectural parameters, like the bit width of ingress and egress ports, number of virtual channels, etc.
- Author: Benny Winefeld, Solutions Architect
