What is AMBA CHI? (Coherent Hub Interface)

Overview

AMBA CHI (Coherent Hub Interface) is a high-performance, scalable cache coherency protocol defined in the Arm AMBA 5 specification. It enables multiple processors, accelerators, and memory systems within a system-on-chip (SoC) to operate on shared data with consistent visibility and ordering guarantees. It is widely used in advanced SoCs, where maintaining coherency across heterogeneous compute elements is critical to system performance.

Why Does AMBA CHI Matter?

As modern SoCs scale to support AI, multi-core processing, and chiplet-based architectures, maintaining data consistency across distributed compute resources becomes increasingly complex. AMBA CHI addresses this challenge by providing a standardized, high-bandwidth coherency framework that ensures all processing elements see the same version of data at the right time.

How Does AMBA CHI Work?

CHI uses a packet-based, layered architecture with protocol and link layers, allowing flexible physical implementation depending on system requirements. It relies on distributed home nodes and request nodes to track data ownership and enforce coherency rules. Requests, responses, and data transfers are handled independently, enabling high concurrency and efficient data movement across the system.

AMBA CHI is also being extended beyond a single die to support chip-to-chip (C2C) communication in multi-die and chiplet architectures. In these systems, coherency must span physical boundaries, enabling distributed compute elements to function as a single, coordinated system. Extending CHI over die-to-die interconnects allows designers to scale performance beyond reticle limits while maintaining a consistent and predictable view of memory. This is an increasingly critical requirement for AI, data center, and automotive platforms.

Benefits of AMBA CHI

• Scalable coherency across many cores and accelerators
• High bandwidth and low latency for data-intensive workloads
• Efficient data sharing across heterogeneous systems
• Support for advanced AI and multi-die architectures

Common Use Cases

• AI and machine learning SoCs
• Automotive systems (ADAS and autonomous driving)
• Data center processors and networking chips
• Multi-die and chiplet-based systems

AMBA CHI in System Architecture

AMBA CHI defines coherency behavior and communication protocols, but not the topology or physical implementation of data movement. In complex SoCs, that responsibility falls to the interconnect.

A coherent network-on-chip (NoC) translates CHI’s coherency model into efficient, predictable data movement across CPUs, accelerators, and memory. It manages traffic and efficiently implements CHI coherency mechanisms, ensuring performance scales with system size.

Arteris Ncore is designed to implement and scale AMBA CHI-based coherency across heterogeneous, high-bandwidth systems. It implements and scales CHI-based coherency, including traffic management, QoS, and data movement across multiple domains and multi-die architectures.

As SoCs become more distributed, CHI defines the rules, but the NoC determines how well those rules perform in practice.