Compute Express Link (CXL) Explained

What is Compute Express Link (CXL)?

Compute Express Link (CXL) is an open interconnect standard that enables processors, accelerators, memory devices, and other system components to communicate using a coherent memory model. Built on the PCI Express (PCIe) physical layer, CXL adds capabilities that help systems share memory more efficiently and move data between compute resources with lower overhead.

Why does CXL matter?

CXL is important to data center architects because it helps change memory from a fixed resource inside one server into a more flexible infrastructure resource. That flexibility is increasingly important as AI, cloud, analytics, and high-performance computing workloads demand larger memory footprints, faster access to data, and better utilization across heterogeneous systems.

Modern data centers are often limited by how efficiently memory can be accessed, shared, and scaled, rather than the amount of compute available. Large language models, AI training clusters, inference systems, databases, and HPC applications can leave memory stranded in some servers while other systems are capacity constrained.

CXL helps address these challenges by enabling:

• Memory expansion beyond traditional server memory limits
• Memory pooling to improve utilization and reduce stranded capacity
• More flexible accelerator and memory architectures
• Sharing of memory between accelerators and general-purpose processors
• A foundation for composable and disaggregated infrastructure
• The result is not simply more memory. It is a more adaptable data center architecture that can better match memory resources to workload needs.

How does CXL work?

CXL uses the PCIe physical interface while adding protocols for coherent communication between hosts and attached devices. The core protocol set includes: 

• CXL.io for configuration, discovery, device management, and I/O communication
• CXL.cache for coherent access to host memory by attached devices, and coherent access to accelerator memory by the host
• CXL.mem for host access to memory attached to CXL devices

Together, these protocols allow CPUs, accelerators, and memory devices to operate with a more consistent view of memory. This is important for systems that need to share data across compute engines without excessive copying or inefficient software-managed movement.

Types of CXL devices

CXL defines several device types that support different architectural roles.

• Type 1 devices are accelerators that use coherent access to host memory but do not include local device memory.
• Type 2 devices are accelerators with local memory, such as GPUs, AI accelerators, or other compute devices that need coherence with the host.
• Type 3 devices are memory expansion or memory pooling devices that provide additional capacity to one or more hosts.

For data center infrastructure, Type 3 devices are especially important because they enable memory capacity to be expanded and pooled beyond the limits of a single server.

CXL vs PCIe

CXL and PCIe are closely related, but they are not the same. PCIe provides the physical transport and a widely adopted device connectivity model. CXL builds on that foundation by adding memory semantics and coherence capabilities that are critical for shared memory architectures.

In practice, PCIe remains essential to the platform, while CXL extends what the platform can do with memory and accelerators. CXL.io is essentially PCIe with some additional capabilities. PCIe connects devices and CXL helps those devices participate in a more coherent, memory-centric system.

CXL in modern data centers

CXL is becoming important as data centers move toward more heterogeneous and composable architectures. Instead of building every server with enough memory for peak demand, architects can use CXL-enabled systems to expand or pool memory so resources can be allocated more efficiently.

Common data center applications include: 

• AI training and inference systems
• Cloud infrastructure
• HPC environments
• Memory expansion appliances
• Composable infrastructure deployments

These use cases share a common requirement: large volumes of data must be placed close enough to compute resources to support performance without locking resources into inefficient fixed configurations.

CXL, chiplets, and coherent fabrics

CXL is also part of a broader architectural shift toward coherent fabrics, chiplets, and heterogeneous compute. As systems combine CPUs, GPUs, NPUs, custom accelerators, memory devices, and I/O resources, coherent communication becomes more important across multiple layers of the platform.

CXL addresses coherence and memory sharing at the system and rack level. Chiplet interconnects and on-chip fabrics address communication inside packages and SoCs. Together, these technologies reflect the same larger trend: modern computing performance depends on how efficiently data moves across increasingly distributed compute resources.

The relationship between CXL and network-on-chip architecture

CXL can expand memory capacity and improve sharing between hosts, accelerators, and memory devices, but the data must still move efficiently inside each chip. Within the SoC, network-on-chip (NoC) architectures route traffic between CPUs, GPUs, NPUs, caches, memory controllers, and I/O subsystems.

As CXL-enabled systems increase memory availability and connect more heterogeneous resources, on-chip traffic can become more complex. NoC architectures help manage congestion, preserve bandwidth, support quality of service, and scale communication across large SoCs. CXL helps extend memory flexibility outside the chip; NoC technology helps ensure the chip can use that flexibility efficiently.

CXL and Arteris

Arteris interconnect IP helps semiconductor designers build scalable SoCs that support the data movement demands of AI, cloud, HPC, and data center architectures. FlexNoC, FlexGen, and Ncore help connect processors, accelerators, caches, memory controllers, and I/O subsystems while supporting bandwidth, latency, and quality of service requirements.

As CXL changes how memory and accelerators are connected at the platform level, efficient on-chip communication becomes even more important. Arteris helps designers optimize internal data movement so complex SoCs can take advantage of advanced memory and system-level architectures.