Data movement in modern SoCs

What is data movement?

In modern systems-on-chip (SoCs) and chiplet-based architectures, data movement refers to the transport of information between processing elements, on-chip caches, shared memories, I/O peripherals, and external memory interfaces via the on-chip interconnect fabric. This includes transactions, cache lines, and memory reads or writes.

As SoCs scale to include tens or hundreds of heterogeneous cores, multiple memory hierarchies, and multi-die configurations, the cost of data movement increases the overall cost. Industry analyses show that data movement can consume up to 80% of total SoC energy, far exceeding the cost of arithmetic operations.

Every additional hop, router stage, or wire segment contributes to latency, power consumption, and routing congestion, often determining system-level performance and energy efficiency more than the compute units themselves.

In short, data movement has become a fundamental bottleneck in advanced SoCs and chiplet systems, affecting energy efficiency, latency, and scalability.

Why it matters

Energy and power efficiency

Every bit transferred across on-chip wires and routers consumes dynamic and leakage power. With advanced nodes and long interconnect lengths, wire energy becomes a dominant contributor to total dynamic power.

Optimizing data movement by reducing wirelength, router count, and congestion directly reduces system-level power consumption.

Arteris customers, such as Samsung, report using Arteris FlexNoC® to reduce power and die area in SoCs with more than 100 IP blocks. Furthermore, industry studies show ~25–30% latency and power improvements over legacy bus architectures.

Latency and throughput

High hop counts, congestion, and suboptimal routing degrade throughput. For AI, real-time vision and memory-bound workloads, delays compound across billions of operations.

Mobileye notes that Arteris FlexNoC enables high-bandwidth communication and load-balanced traffic to memory, simplifying timing closure.

The physically aware Arteris network-on-chip (NoC) synthesis shortens critical paths and improves timing closure, even in high-frequency SoCs.

Routing congestion and wire count

Traditional point-to-point interconnects dramatically increase wire count as IP scales.

An Arteris NoC can reduce total wire length by up to 50%, thereby lowering congestion hotspots and improving layout convergence.

Scalability and iteration speed

Manual interconnect design does not scale. Automated topology generation accelerates iteration and improves physical convergence.

The FlexGen Smart NoC IP can reduce interconnect design cycles by up to 10 times, automating wirelength, timing, and power optimization.

How Arteris addresses data movement

Protocol-agnostic transport via NIUs

Each IP connects through a network interface unit (NIU), which translates local protocols such as AXI, AHB, CHI, or OCP into a packetized transport layer. This decouples protocol from transport, enabling plug-and-play integration and easier reuse across designs.

Physically aware, timing-driven topologies

FlexNoC 5 integrates with physical design tools, incorporating floorplan constraints, wirelengths, and timing data. This reduces wire length, buffer count, and ECO loops, often shortening backend timing closure by weeks. Arteris reports a wirelength reduction of up to 30% in large AI and automotive SoCs.

AI-assisted topology generation

FlexGen Smart NoC utilizes AI-driven search to explore topology options, thereby minimizing latency, congestion, and wire overhead. This enables up to 10× faster iteration and higher-quality architectures for AI and automotive systems.

Modular, tiled scalability

Arteris supports tiled or modular NoC construction ideal for GPU/NPU arrays and multi-cluster CPU complexes. Regular topologies simplify verification, reduce integration risk, and support incremental scaling across dies.

QoS, virtual channels, and traffic isolation

FlexNoC embeds QoS controls, virtual channels, and congestion management to prevent traffic interference. This ensures predictable latency and bandwidth for real-time, automotive, and AI workloads.

Integration with caching and coherency

Ncore coherent interconnect and CodaCache work with the NoC to reduce unnecessary data movement. By reusing data locally and filtering snoops, they minimize off-chip memory access, reducing both bandwidth and power.

When data movement optimization is critical

AI and machine learning workloads

AI inference and training are primarily driven by memory movement rather than arithmetic operations. Optimized NoC fabrics can double effective throughput by removing memory bottlenecks.

Arteris solutions are deployed in Mobileye’s autonomous vision SoCs and leading AI accelerators.

Chiplet and multi-die systems

As designs partition across dies, die-to-die interconnect efficiency becomes critical. Arteris supports multi-die topologies that integrate with UCIe and interposer links to minimize latency and power penalties.

Heterogeneous systems and many IP blocks

Modern SoCs contain hundreds of IP cores, while modular NoCs simplify connectivity and incremental scaling without global redesign.

High-frequency and tight timing budgets

Physically aware NoC synthesis and hierarchical floor planning enable timing closure above 1 GHz while keeping congestion manageable.