What is UCIe? (Universal Chiplet Interconnect Express)

Universal Chiplet Interconnect Express (UCIe) is an open industry standard that defines how chiplets communicate within a multi-die package. It provides a common, high-bandwidth, low-latency interface that allows multiple dies to function as a unified system, enabling scalable, modular SoC design.

Why Does UCIe Matter?

As SoCs evolve beyond monolithic designs, chiplets offer a practical path to scaling performance, yield, and flexibility. However, without a standardized interface, integrating chiplets from different sources introduces complexity and risk. UCIe addresses this by establishing a consistent, interoperable framework for die-to-die communication.

For AI, data center, and automotive systems, where performance demands and design complexity are rapidly increasing, UCIe enables architects to partition functionality across multiple dies while maintaining system-level efficiency.

How Does UCIe Work?

UCIe defines a layered architecture that separates protocol, adapter, and physical layers, allowing flexibility in implementation while maintaining interoperability.
It supports two primary modes:

• Standard package: optimized for cost and power efficiency on organic substrates.
• Advanced package: optimized for high-performance implementations such as silicon interposers or advanced packaging technologies.

UCIe can transport multiple protocols, including PCIe and CXL, while also supporting streaming and memory-semantic traffic. This flexibility allows designers to reuse existing ecosystems while enabling new chiplet-based architectures.

Benefits of UCIe

• Enables scalable and reusable chiplet-based system design
• Promotes interoperability across vendors and ecosystems
• Reduces development risk and integration complexity
• Supports high-bandwidth, low-latency communication between dies
• Extends Moore’s Law through modular system scaling

Common Use Cases

• AI and machine learning accelerators
• Data center processors and infrastructure silicon
• Automotive and advanced driver assistance systems (ADAS)
• High-performance computing (HPC) platforms
• Multi-die and chiplet-based SoCs

UCIe in System Architecture

UCIe defines how chiplets connect, but it does not define how data moves efficiently across the system. That responsibility sits with the interconnect architecture.

In complex SoCs, a network-on-chip (NoC) manages traffic between compute, memory, and I/O resources, ensuring performance, scalability, and quality of service. When extended into multi-die systems, the NoC must coordinate traffic not only within a die, but across chiplet boundaries through interfaces like UCIe.

Arteris interconnect IP enables this system-level coordination by managing data movement across heterogeneous compute elements and multiple dies. By combining UCIe-based connectivity with intelligent NoC design, architects can scale performance while maintaining predictable latency, bandwidth, and system behavior.

Frequently Asked Questions

What is the purpose of UCIe?
UCIe provides a standardized interface for connecting chiplets within a package, enabling modular SoC design and reducing integration complexity.

How is UCIe different from PCIe or CXL?
PCIe and CXL are system-level interconnect protocols, while UCIe defines the physical and protocol layers for die-to-die communication within a package. UCIe can transport PCIe and CXL traffic across chiplets.

Is UCIe used for chiplet architectures?
Yes. UCIe is specifically designed to enable chiplet-based systems by providing a common interface for die-to-die connectivity.

Does UCIe replace NoC technology?
No. UCIe complements NoC technology. While UCIe connects chiplets, the NoC manages how data moves within and across those chiplets over the UCIe physical layer to ensure system-level performance.

Why is UCIe important for AI systems?
AI systems require massive bandwidth and scalability. UCIe enables designers to distribute compute and memory across multiple dies while maintaining efficient communication, which is critical for performance and power efficiency.