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Semiconductor Engineering: Optimizing NoC-Based Designs

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Semiconductor Engineering article:

Optimizing NoC-Based Designs

May 5th, 2022 - By Paul Graykowski

Further optimization of RTL repartitioning with switching from crossbar interconnects to NoCs.

Semiconductor development is currently in a phase of rapid evolution driven by the combination of new technologies and methodologies. The technique of combining multiple functions into systems-on-chips (SoCs) is continuing to grow in complexity. Rapid advancement in new technologies for market segments like data centers, robotics, ADAS and artificial intelligence/machine learning (AI/ML) are resulting in a new breed of SoCs. These fields demand designs that are maximized for both power and performance efficiency. Designers are finding that networks-on-chip (NoCs) provide the enabling technology to meet this demand and are accelerating the move away from crossbar interconnect technology.

Learn more about Arteris IP Deployment Technology Products .

 

Topics: network-on-chip timing closure ADAS semiconductor engineering latency bandwidth SoCs congestion logic RTL data centers AI/ML NoCs floorplan Arteris IP (AIP) Paul Graykowski partitioning physical design crossbar interconnect robotics

Sondrel Deploys Arteris IP for Next-Generation Multi-Channel Automotive SoC

Configurability and Performance of FlexNoC is Key to Design of High-Performance Compute IP Platform for ADAS Applications

READING, UK and CAMPBELL, Calif. – May 3, 2022 -- Sondrel and Arteris IP (Nasdaq: AIP), a leading provider of system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate system-on-chip (SoC) creation, today announced that Sondrel is adopting FlexNoC interconnect IP in its next generation of advanced driver-assistance systems (ADAS) architecture. The onchip-interconnect was selected for its configurability and performance. The product enables the SFA 350A multi-channel automotive vehicle IP platform requirements. FlexNoC supports the ability to design the NoC to match the performance of IP blocks to ensure that data flows at the right speed in, out and around the SoC. It enables designers to quickly design and verify a chip that precisely meets the customer’s silicon specifications on time and within budget.

 

Through many years of working with Arteris, we knew that FlexNoc would reliably deliver exactly what we needed, backed up by excellent technical support. The SoC interconnect provides a complete, comprehensive solution spanning architecture exploration to physical implementation and verification."


Edwin Loverseed, Head of Engineering, Sondrel

 

Topics: IP System-on-Chip NoC ISO 26262 Networks-On-Chip Arteris FlexNoC automotive ADAS radar soc architecture verification LIDAR SoCs high-performance sensors ASIC ip deployment Arteris IP (AIP) SFA 350A processor silicon chips compute solutions Edwin Loverseed

Arteris IP's Stefano Lorenzini to Speak at Automotive IQ Application of ISO 26262 Berlin Conference

CAMPBELL, Calif. – April 25, 2022 – Arteris IP (NASDAQ: AIP), a leading provider of system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate system-on-chip (SoC) creation, today announced that Functional Safety Manager Stefano Lorenzini will present at the Automotive IQ Application of ISO 26262 Conference on Wednesday, April 27, 2022, at Hilton Berlin, Germany. His keynote presentation, Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip, begins at 11:15 (CEST).

Topics: SoC System-on-Chip NoC functional safety ISO 26262 SoC design Networks-On-Chip soc architecture arteris ip functional safety manager FMEDA IEC 61508 ip deployment Stefano Lorenzini AIP Berlin Conference Automotive IQ

Claudia Fan Munce Joins Arteris IP Board of Directors

Veteran executive, Stanford lecturer and public company board member brings decades of relevant international corporate experience to Arteris IP

CAMPBELL, Calif. – April 5, 2022 – Arteris IP (NASDAQ: AIP), a leading provider of system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate system-on-chip (SoC) creation, today announced that Claudia Fan Munce will join Arteris IP’s Board of Directors and will commence her service at the company’s May 2022 board and committee meetings.

 

I’m very excited to welcome Claudia Fan Munce with her publicly traded company board stewardship and technology management experience to guide Arteris to the next stage in achieving our goals."


K. Charles Janac, President and CEOArteris IP

Topics: SoC System-on-Chip NoC network-on-chip K. Charles Janac Board of Directors Arteris IP (AIP) Best Buy Corporation BNP Paribas Christian Claussen Claudia Fan Munce IBM New Enterprise Associates Bank of the West Stanford University

Arteris® IP FlexNoC® Interconnect and Resilience Package Licensed in Neural Network Accelerator Chip Project Led by BMW Group

NoC interconnect IP to be dataflow backbone of German Federal Ministry of Education and Research (BMBF) project chip to advance automotive artificial intelligence and machine learning (AI/ML) processing.

CAMPBELL, Calif. – April 5, 2022 – Arteris IP (NASDAQ: AIP), a leading provider of system-on-chip (SoC) system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate SoC creation, today announced that BMW Group has licensed FlexNoC interconnect IP and the accompanying FlexNoC Resilience Package IP for use in a chip partially funded by the German Federal Ministry of Education and Research (BMBF) as part of the ZUSE-KI-mobil publicly funded project. The goal of the project is to develop an accelerator chip for high-end deep learning applications that is a leap forward in terms of energy efficiency, reliability, robustness and security, which go far beyond current possibilities. BMW Group is serving as the coordinator and leader of the project.

We are excited that the consortium led by BMW Group chose Arteris IP interconnect technology as the on-chip communications on-chip network for this innovative automotive system-on-chip. BMW Group’s decision to use our interconnect IP as the dataflow on-chip network of this complex system is a testimony to the benefits our technologies bring to design teams creating the world’s most sophisticated AI/ML processing chips."


K. Charles Janac, President and CEO, Arteris IP

Topics: System-on-Chip functional safety Arteris FlexNoC automotive flexnoc resilience package reliability machine learning artificial intelligence neural network AI latency SoCs power efficiency noc interconnect on-chip communications dataflow Arteris IP FlexNoC interconnect AI/ML ip deployment mobile usage IP blocks system ip Arteris IP (AIP) BMW Group ZUSE-KI-mobil processing chips BMBF

Michal Siwinski Joins Arteris IP as Chief Marketing Officer

Proven executive with extensive EDA, IP and semiconductor experience to lead the company through its next growth stage.

CAMPBELL, Calif. – March 22, 2022 – Arteris IP (NASDAQ: AIP), a leading provider of system-on-chip (SoC) system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate SoC creation and process flow, today announced that Michal Siwinski has joined the company as its Chief Marketing Officer. He will have worldwide responsibility for all marketing functions and partnership management. As a vital member of the executive team, Mr. Siwinski will report to K. Charles Janac, Arteris IP President and CEO.

 

We are honored to welcome Michal Siwinski to our executive team. Michal has the right combination of public company experience, strategic vision, technical know-how, marketing panache and extensive experience developing transformational and visionary marketing strategies. His proven track record of accelerating growth and enabling collaborative innovation will help take Arteris IP to the next level, delivering industry-leading solutions to semiconductor and system companies."


K. Charles Janac, President and CEOArteris IP

Topics: SoC semiconductor IP Cadence NoC K. Charles Janac EDA system ip Arteris IP (AIP) IP development software CMO B2B Verplex Systems Mentor Graphics UC Berkeley Chief Marketing Officer Michal Siwinski

Electronic Design Article: Making ISO 26262 Traceability Practical


This Electronic Design article, 'Making ISO 26262 Traceability Practical', covers Arteris IP's Harmony Trace in this piece authored by Paul Graykowski, Senior Technical Marketing Manager. 

March 4 , 2021 - By Paul Graykowski

The ISO 26262 standard states that functional-safety assessors should consider if requirements management, including bidirectional traceability, is adequately implemented. The standard doesn’t specify how an assessor should go about accomplishing this task. However, it’s reasonable to assume that a limited subset of connections between requirements and implementation probably doesn’t rise to the expectation.

 

For more information about Arteris Harmony Trace please visit: https://www.arteris.com/harmony-trace-design-data-intelligence

 

Topics: NoC functional safety ISO 26262 network-on-chip autonomous vehicles ip-xact SoCs AI chips EDA electronic design traceability Arteris IP (AIP) Arteris Harmony Trace Paul Graykowski HSI PLM ALM

Semiconductor Engineering: Where Do Memory Maps Come From?

Guillaume Boillet, Senior Director of Product Management at Arteris IP authored this Semiconductor Engineering article:

Where Do Memory Maps Come From?

March 3rd, 2022 - By Guillaume Boillet

Ensuring software can accurately address hardware.


A memory map is the bridge between a system-on-chip (SoC) and the firmware and software that is executed on it. Engineers may assume the map automatically appears, but the reality is much more involved. The union of hardware (HW) and software (SW) demands both planning and compromise. The outcome of this merger will not be fully realized until the magical day when the system comes to life.

To learn more about SoC and Hardware/Software Interface (HSI) Development, please download this datasheet:  SoC & Hardware / Software Interface (HSI) Development Datasheet 

 

Topics: software network-on-chip power time to market semiconductor engineering arteris ip hardware SoCs EDA Guillaume Boillet NoCs Arteris IP (AIP) HSI addresses embedded firmware memory map

SemiWiki: An Ah-Ha Moment for Testbench Assembly

Bernard Murphy (SemiWiki) gets an update from Arteris IP.

An Ah-Ha Moment for Testbench Assembly 

February 28, 2022 - Bernard Murphy

Sometimes we miss the forest for the trees, and I’m as guilty as anyone else. When we think testbenches, we rightly turn to UVM because that’s the agreed standard, and everyone has been investing their energy in learning UVM. UVM is fine, so why do we need to talk about anything different? That’s the forest and trees thing. We don’t need to change the way we define testbenches – the behavior and (largely) the top-level structure. But maybe there’s a better way to assemble that top level through a more structured assembly method than through hand-coding or ad-hoc scripting. Still built on UVM at leveraging the standardization benefits of IP-XACT for assembly around VIPs.
 
Topics: SoC NoC network-on-chip semiconductor arteris ip semiwiki ip-xact RTL UVM noc interconnect test bench assembly Arteris IP Harmony Trace Paul Graykowski Jama software SoC verification Magillem UTG UVM Testbench Generator Arteris (AIP)

Design & Reuse: Traceability for Embedded Systems

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Design & Reuse article:

Traceability for Embedded Systems

February 3rd, 2022 - By Paul Graykowski

Maintaining connection between requirements and implementation is where traceability for embedded systems can show value. 

 

In an embedded system, the hardware/software interface (HSI) is a representation of requirements between hardware and software development teams. This description elaborates a huge wealth of detail in memory and IP register offsets, bitfields and detailed behavior specifications. In this representation, at least some aspects must be met precisely. This expectation is especially important because many designs must work with legacy software, not only to minimize development time but also to preserve reliability. A new device replacing one from a different vendor must often mirror all or most of the original HSI. In this context, capturing those requirements and using traceability to track compliance through development becomes a clear advantage.

To learn more about traceability and Arteris Harmony Trace, please download this technical paper: https://www.arteris.com/download-reinventing-traceability-arteris-harmony-trace-paper

Topics: network-on-chip arteris ip verification SoCs RTL UVM compliance EDA traceability NoCs Arteris IP (AIP) validation Arteris Harmony Trace Paul Graykowski Design&Reuse HSI