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Kurt Shuler

Kurt Shuler

Recent Posts by Kurt Shuler:

Semiconductor Engineering: IC Security Threat Grows As More Devices Are Connected

Guillaume Boillet, Director of Product Management at Arteris IP is quoted in this new article in Semiconductor Engineering:

IC Security Threat Grows As More Devices Are Connected 

May 6th, 2021 - By Ann Steffora Mutschler

Awareness increases, but so does the complexity of systems and the potential attack surface.

 “We would expect this industry to be adopting cloud-based software-as-a-service massively, but the reality is different,” said Guillaume Boillet, director of product management at Arteris IP. “The design environment itself is almost always in a customer-owned data center. There has been some push to leverage the benefits of the cloud, and of course it’s very appealing because now you can scale your data centers. But I don’t have an example where, all of a sudden, you’ve got a need for more computing power and you would rather rely on the cloud than build a rack. This is not happening for multiple reasons. One, people are very protective of their IP, of what they’re doing, so it’s been an hindrance for us in terms of support, etc. Also, moving to the SaaS model requires a total rethink of the licensing, because it’s a totally different monetization scheme. I’ve seen examples where this scenario would have required a lot of work and a lot of revamping of the toolset.”

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip interconnects datacenters security Guillaume Boillet ecosystem security

Semiconductor Engineering: NoCs In Authoritative MPSoC Reference

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article in Semiconductor Engineering:

NoCs In Authoritative MPSoC Reference

May 6th, 2021 - By Kurt Shuler

The role of the network-on-chip in ensuring total system safety.

K. Charles Janac, president and CEO of Arteris IP, authored the first chapter in that third section on network-on-chip (NoC) architecture and how it has enabled MPSoCs. 

The chapter starts with the evolution from buses to crossbars to NoCs. Next is a useful overview of a typical approach to architecting and configuring a NoC. As the most configurable intellectual property (IP) in an SoC, getting the design to an optimal solution requires careful planning and refinement. The design evolves, not just the logic but also the topology.

By the way, this book is a technical review, not a marketing pitch. Charlie is quite open that while NoCs share some concepts with “regular” communications networks, the analogy cannot be stretched too far. NoC design is still very much an activity for semiconductor designers, not general network designers.

Topics: SoC NoC functional safety network-on-chip ECC cache coherency IEEE semiconductor engineering arteris ip ASIL D K. Charles Janac interconnects kurt shuler ai accelerators security TMR MPSOC LBIST

Semiconductor Engineering: Steep Spike For Chip Complexity And Unknowns

K. Charles Janac, CEO at Arteris IP is quoted in this new Semiconductor Engineering article:

Steep Spike For Chip Complexity And Unknowns

May 5th, 2021 - By Ed Sperling

Increased interactions and customizations drive up risk of re-spins or failures.

“There are several aspects that need to be considered, such as making sure the customer is using the right version of the IP,” said K. Charles Janac, chairman and CEO of Arteris IP. “You’re basically enforcing that the IP-XACT parameters are there in order for the IP block to be admitted into the SoC. There’s also the aspect of supply management. Many of these companies have a layout house, a design house, and foundry contractors. If that entire supply chain is IP-XACT — from the interaction between the various parties in the supply chain to what ultimately provide what goes into the SoC — it gets much, much smoother. At the same time, you are going to have some pieces of the chip that are on the leading-edge process and some on the trailing edge, such as analog.

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip K. Charles Janac ip-xact interconnects chiplets inter-chip IPD

Semiconductor Engineering: Security Concerns Rise For Connected Autos

K. Charles Janac, CEO at Arteris IP is quoted in this new Semiconductor Engineering article:

Security Concerns Rise For Connected Autos

April 29th, 2021 - By John Koon

Value of automotive data increases, widening the attack surface.

“We’re seeing a shift in the entire automotive industry, essentially from mechanics to electronics being the core competence of the automotive industry,” said K. Charles Janac, chairman and CEO of Arteris IP. “This includes either influence on architectures or IP design, or maybe even doing entire SoCs, by the car companies and by the Tier 1s, because you need to control your architecture in order to enforce upgradability.”

Topics: SoC NoC network-on-chip ADAS autonomous vehicles semiconductor engineering arteris ip K. Charles Janac interconnects 5G automotive security ISO 21434

SemiWiki: Arteris IP Contributes to Major MPSoC Text

Bernard Murphy of (SemiWiki) comments on a recent book release on MPSoC design. 

Arteris IP Contributes to Major MPSoC Text

April 29th, 2021 - Bernard Murphy

You might have heard of the Multicore and Multiprocessor SoC (MPSoC) Forum sponsored by IEEE and other industry associations and companies. This group of top-notch academic and industry technical leaders gets together once a year to talk about hardware and software architecture and applications for multicore and multiprocessor systems-on-chip (SoCs). They gather to debate the latest and greatest ideas to meet emerging needs.
 
K. Charles Janac, president and CEO of Arteris IP, wrote the first chapter in the third section on network-on-chip (NoC) architectures. I’m impressed that what must be considered a definitive technical reference on MPSoCs required a chapter on NoC interconnect, and the editors turned to Arteris IP to write that chapter.
Topics: SoC NoC ISO 26262 network-on-chip semiconductor AI semiwiki K. Charles Janac kurt shuler noc interconnect cache coherence MPSoC Forum

Arteris IP Welcomes Back Veteran Laurent Moll as Chief Operating Officer

As a top industry executive, holding prior roles at Qualcomm and NVIDIA, Moll Brings strategic leadership as the company drives system-on-chip IP integration growth.

CAMPBELL, Calif. – April 14, 2021 – Arteris IP, a leading provider of network-on-chip (NoC) interconnect and other intellectual property (IP) technology that manages the on-chip communications in system-on-chip (SoC) semiconductor devices, today announced it is proud to welcome Laurent Moll as Chief Operating Officer (COO). Laurent will be responsible for managing all aspects of engineering functions and operations at Arteris IP. He will participate in the company’s growth strategies and oversee the successful delivery of its industry-leading semiconductor designs as Arteris IP increases in scope and market share.

We are excited to welcome Laurent back to our team at Arteris IP. Laurent will not only bring his expertise and experience to focus on our company's technology evolution but will also provide additional leadership to solidify our SoC integration IP position.”


K. Charles Janac, President and CEOArteris IP

Topics: SoC NoC laurent moll on-chip interconnect automotive nvidia K. Charles Janac IP market COO qualcomm system-on-chip development

Arteris® IP Adds a Record 28 New Licensees in 2020

Network-on-Chip (NoC) semiconductor IP growth driven by customer development of new automotive, machine learning, 5G & data center system-on-chip (SoCs).

CAMPBELL, Calif. – February 17, 2021 – Arteris IP, a leading provider of network-on-chip (NoC) interconnect and other intellectual property (IP) technology that manages the on-chip communications in system-on-chip (SoC) semiconductor devices, today announced that the company added 28 new licensees for its Arteris® IP Ncore®, FlexNoC®, CodaCache®, AI Package, Resilience Package, and PIANO® Interconnect IP products in 2020. With the addition of these 28 new licensees, the cumulative number of Arteris IP semiconductor IP licensees throughout the company’s history reached 159. SoC design starts throughout the company’s history exceeded 500 chip projects. Furthermore, two large semiconductor vendor customers signed multi-year licensing deals with the company.

Despite the COVID headwinds, Arteris IP had a strong year based on both technology delivery and customer acquisition gains. Our focus on automotive, machine learning, 5G and data center applications has provided increased competitive value to our customers, who rewarded Arteris IP with an unprecedented number of SoC design wins.”


K. Charles Janac, President and CEOArteris IP

Topics: SoC NoC on-chip interconnect automotive AI K. Charles Janac ip-xact ML 5G IP market Isabelle Geday IP Deployment Division Board of Directors IPDD data center systems-on-chip GUI Tcl

Arteris® IP Adds Two Veteran Executives to its Board of Directors

Network-on-Chip (NoC) semiconductor IP leader adds Raman Chitkara and Isabelle Geday to its Board of Directors 

CAMPBELL, Calif. – February 10, 2021 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Raman Chitkara and Isabelle Geday have joined its Board of Directors.

I am excited to be working with board members of Raman's and Isabelle's caliber and talent. With Raman's knowledge of accounting best practices and Isabelle's strong European and software management experience, we have a skilled and knowledgeable team of board members who will help navigate the evolution of Arteris IP.”


K. Charles Janac, President and CEOArteris IP

Topics: SoC NoC on-chip interconnect AI K. Charles Janac ML IP market Isabelle Geday IP Deployment Division Raman Chitkara Board of Directors

Arteris® IP FlexNoC® Interconnect and Resilience Package Supports Socionext's 5nm Automotive Chip Production

Automotive chip design leader standardizes on Network-on-Chip (NoC) interconnect IP for multiple ISO 26262-compliant systems-on-chip (SoCs)

CAMPBELL, Calif. and YOKOHAMA, Japan– February 4, 2021 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Socionext has implemented Arteris® FlexNoC® interconnect IP and the accompanying Resilience Package in multiple automotive chips, including an automotive SoC fabricated using 5nm semiconductor process technology.

We are able to more efficiently design large scale automotive chips because we are able to see early in the design process the layout impacts of our SoC and NoC architecture choices. This is especially important when using leading edge 5nm semiconductor process technologies. Furthermore, our SoC functional safety architecture has been enhanced by the novel technologies in the FlexNoC interconnect IP Resilience Package, allowing us to quickly tailor safety mechanisms for the desired ISO 26262 ASIL to meet our customers’ demanding schedules."


Kaichi Yamashita, Head of the Automotive Business Unit, Socionext

Topics: SoC NoC functional safety network-on-chip on-chip interconnect flexnoc resilience package ADAS iso 26262 ASIL K. Charles Janac customer automotive chips IP market Socionext 5nm

Arteris® IP FlexNoC® Interconnect and Resilience Package Licensed by Hailo for Artificial Intelligence (AI) Chip

Leading AI chipmaker Hailo uses world-leading network-on-chip (NoC) IP to accelerate dataflow performance

CAMPBELL, Calif. – January 12, 2021 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Hailo has licensed FlexNoC Interconnect IP and the accompanying Resilience Package for use in Hailo’s AI processor targeting automotive, smart cities, smart retail, Industry 4.0 and other markets.

The Arteris IP FlexNoC interconnect is much more efficient than competitive technologies. The state-of-the-art interconnect IP reduces the die area and power consumption of our unique architecture, which helps us to meet the market requirements."


Orr Danon, CEO, Hailo

Topics: SoC NoC network-on-chip on-chip interconnect flexnoc resilience package K. Charles Janac kurt shuler customer IP market hailo ai processor smart cities