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Madelyn Miller

Madelyn Miller

Recent Posts by Madelyn Miller:

Semiconductor Engineering: Many Chiplet Challenges Ahead

Michael Frank, fellow and system architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Many Chiplet Challenges Ahead

April 12th, 2021 - By Brian Bailey

Assembling systems from physical IP gaining mindshare, but there are technical, business and logistical issues that need to be resolved before this will work.

“The size of the bits and pieces is an issue,” says Michael Frank, fellow and system architect at Arteris IP. “It is perhaps less of an issue with chiplets or 2.5D, where things are mounted on a substrate, but it adds additional challenges for 3D. We are no longer dealing with gravel. It is grains of sand, or even dust specs. It’s more robust to build boards.”

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip interconnects chiplets Michael Frank 5nm ESD

Arteris IP Welcomes Back Veteran Laurent Moll as Chief Operating Officer

As a top industry executive, holding prior roles at Qualcomm and NVIDIA, Moll Brings strategic leadership as the company drives system-on-chip IP integration growth.

CAMPBELL, Calif. – April 14, 2021 – Arteris IP, a leading provider of network-on-chip (NoC) interconnect and other intellectual property (IP) technology that manages the on-chip communications in system-on-chip (SoC) semiconductor devices, today announced it is proud to welcome Laurent Moll as Chief Operating Officer (COO). Laurent will be responsible for managing all aspects of engineering functions and operations at Arteris IP. He will participate in the company’s growth strategies and oversee the successful delivery of its industry-leading semiconductor designs as Arteris IP increases in scope and market share.

We are excited to welcome Laurent back to our team at Arteris IP. Laurent will not only bring his expertise and experience to focus on our company's technology evolution but will also provide additional leadership to solidify our SoC integration IP position.”


K. Charles Janac, President and CEOArteris IP

Topics: SoC NoC laurent moll on-chip interconnect automotive nvidia K. Charles Janac IP market COO qualcomm system-on-chip development

Semiconductor Engineering: More Data Drives Focus On IC Energy Efficiency

Michael Frank, fellow and system architect at Arteris IP are quoted in this new Semiconductor Engineering article:

More Data Drives Focus On IC Energy Efficiency

April 8th, 2021 - By Ann Steffora Mutschler

Decisions that affect how, when, and where data gets processed.

"On the chip side, it’s an engineering discipline. On the other side are the algorithm experts who understand what the masks are and what they want to do,” said Michael Frank, fellow and system architect at Arteris IP.

Topics: SoC NoC network-on-chip machine learning neural networks semiconductor engineering arteris ip interconnects chiplets Michael Frank memory architecture TensorFlow

Semiconductor Engineering: Interconnects In A Domain-Specific World

Kurt Shuler, Vice President of Marketing and Guillaume Boillet, Director of Product Management at Arteris IP are quoted in this new Semiconductor Engineering article:

Interconnects In A Domain-Specific World

April 8th, 2021 - By Brian Bailey

When and where tradeoffs between efficiency and flexibility make sense.

"The prediction of power consumption of chips under a given workload is one of the most complex tasks our industry must tackle today,” says Guillaume Boillet, director of product management for Arteris IP

Kurt Shuler, vice president of marketing at Arteris IP says, “You may have 200 things connected to your NoC at the center of the chip. The NoC tool manages all of the meta data for the IP connected to it. Back-figuring all that information is a huge source of systematic errors. We all make mistakes. And that causes problems, not just for regular chips. But can you imagine that for typical functional safety requirements?”

Topics: SoC NoC functional safety network-on-chip neural networks semiconductor engineering arteris ip interconnects kurt shuler power consumption meta data

Semiconductor Engineering: Privacy Protection A Must For Driver Monitoring

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new Semiconductor Engineering article:

Privacy Protection A Must For Driver Monitoring 

April 1st, 2021 - By Ann Steffora Mutschler

Why driver data collected by in-cabin monitoring systems must be included as part of the overall security system.

Privacy and security has to be addressed at every layer, by all parties, said Kurt Shuler, vice president of marketing at Arteris IP. “We’re getting questions from customers asking, ‘You’ve got this interconnect, it’s a network, you have these firewalls, how do I integrate this into my overall security system for my chip?’ They also want to know how to integrate that in the overall security system of that vehicle subsystem, and how to integrate that into the overall security system for the car, and then the network of cars. If I’m GM, I’ve got a whole network of GM cars running around. Where there’s OnStar, I have to protect that data too, and that’s sitting on servers. The OEM is cognizant of this because they know from market forces that if they screw it up, then people aren’t going to trust them. And even though there are IEEE, ISO, and SAE standards, selling security is like selling insurance. Nobody thinks they need it until after the incident happened. The risk is huge here if you don’t do it right, so you should do everything state of the art. However, there’s nothing currently legally forcing that.”

Topics: SoC NoC functional safety ISO 26262 network-on-chip automotive IEEE semiconductor engineering arteris ip interconnects OEMs security driver monitoring

Semiconductor Engineering: SoC Integration Complexity: Size Doesn't (Always) Matter

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new Semiconductor Engineering article:

SoC Integration Complexity: Size Doesn't (Always) Matter

April 1st, 2021 - By Kurt Shuler

Even small IoT designs can have plenty of complexity in architecture and integration.

It’s common when talking about complexity in systems-on-chip (SoCs) to haul out monster examples: application processors, giant AI chips, and the like. Breaking with that tradition, consider an internet of things (IoT) design, which can still challenge engineers with plenty of complexity in architecture and integration. This complexity springs from two drivers: very low power consumption, even using harvested MEMS power instead of a battery, and quick turnaround to build out a huge family of products based on a common SoC platform while keeping tight control on development and unit costs.

Topics: SoC NoC network-on-chip IoT low power semiconductor engineering arteris ip ip-xact interconnects kurt shuler DVFS ip deployment

Arteris® IP Adds a Record 28 New Licensees in 2020

Network-on-Chip (NoC) semiconductor IP growth driven by customer development of new automotive, machine learning, 5G & data center system-on-chip (SoCs).

CAMPBELL, Calif. – February 17, 2021 – Arteris IP, a leading provider of network-on-chip (NoC) interconnect and other intellectual property (IP) technology that manages the on-chip communications in system-on-chip (SoC) semiconductor devices, today announced that the company added 28 new licensees for its Arteris® IP Ncore®, FlexNoC®, CodaCache®, AI Package, Resilience Package, and PIANO® Interconnect IP products in 2020. With the addition of these 28 new licensees, the cumulative number of Arteris IP semiconductor IP licensees throughout the company’s history reached 159. SoC design starts throughout the company’s history exceeded 500 chip projects. Furthermore, two large semiconductor vendor customers signed multi-year licensing deals with the company.

Despite the COVID headwinds, Arteris IP had a strong year based on both technology delivery and customer acquisition gains. Our focus on automotive, machine learning, 5G and data center applications has provided increased competitive value to our customers, who rewarded Arteris IP with an unprecedented number of SoC design wins.”


K. Charles Janac, President and CEOArteris IP

Topics: SoC NoC on-chip interconnect automotive AI K. Charles Janac ip-xact ML 5G IP market Isabelle Geday IP Deployment Division Board of Directors IPDD data center systems-on-chip GUI Tcl

Arteris® IP Adds Two Veteran Executives to its Board of Directors

Network-on-Chip (NoC) semiconductor IP leader adds Raman Chitkara and Isabelle Geday to its Board of Directors 

CAMPBELL, Calif. – February 10, 2021 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Raman Chitkara and Isabelle Geday have joined its Board of Directors.

I am excited to be working with board members of Raman's and Isabelle's caliber and talent. With Raman's knowledge of accounting best practices and Isabelle's strong European and software management experience, we have a skilled and knowledgeable team of board members who will help navigate the evolution of Arteris IP.”


K. Charles Janac, President and CEOArteris IP

Topics: SoC NoC on-chip interconnect AI K. Charles Janac ML IP market Isabelle Geday IP Deployment Division Raman Chitkara Board of Directors

Arteris® IP FlexNoC® Interconnect and Resilience Package Supports Socionext's 5nm Automotive Chip Production

Automotive chip design leader standardizes on Network-on-Chip (NoC) interconnect IP for multiple ISO 26262-compliant systems-on-chip (SoCs)

CAMPBELL, Calif. and YOKOHAMA, Japan– February 4, 2021 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Socionext has implemented Arteris® FlexNoC® interconnect IP and the accompanying Resilience Package in multiple automotive chips, including an automotive SoC fabricated using 5nm semiconductor process technology.

We are able to more efficiently design large scale automotive chips because we are able to see early in the design process the layout impacts of our SoC and NoC architecture choices. This is especially important when using leading edge 5nm semiconductor process technologies. Furthermore, our SoC functional safety architecture has been enhanced by the novel technologies in the FlexNoC interconnect IP Resilience Package, allowing us to quickly tailor safety mechanisms for the desired ISO 26262 ASIL to meet our customers’ demanding schedules."


Kaichi Yamashita, Head of the Automotive Business Unit, Socionext

Topics: SoC NoC functional safety network-on-chip on-chip interconnect flexnoc resilience package ADAS iso 26262 ASIL K. Charles Janac customer automotive chips IP market Socionext 5nm

Arteris® IP FlexNoC® Interconnect and Resilience Package Licensed by Hailo for Artificial Intelligence (AI) Chip

Leading AI chipmaker Hailo uses world-leading network-on-chip (NoC) IP to accelerate dataflow performance

CAMPBELL, Calif. – January 12, 2021 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Hailo has licensed FlexNoC Interconnect IP and the accompanying Resilience Package for use in Hailo’s AI processor targeting automotive, smart cities, smart retail, Industry 4.0 and other markets.

The Arteris IP FlexNoc interconnect is much more efficient than competitive technologies. The state-of-the-art interconnect IP reduces the die area and power consumption of our unique architecture, which helps us to meet the market requirements."


Orr Danon, CEO, Hailo

Topics: SoC NoC network-on-chip on-chip interconnect flexnoc resilience package K. Charles Janac kurt shuler customer IP market hailo ai processor smart cities