Arteris FlexNoC^® IP delivers superior performance, predictable timing closure and flexibility when deployed in advanced platforms.

RA’ANANA, Israel and Campbell, Calif. – July 11, 2022 – Arteris^® Inc (Nasdaq: AIP) - a leading provider of system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate system-on-chip (SoC) creation - today announced that Inuitive - fabless semiconductor company and designer of powerful multi-core processor ICs - has deployed the company’s FlexNoC^® interconnect IP for its next generation of computer vision platforms based on Inuitive’s Vision-on-Chip processors.

The technology addresses connectivity and timing closure challenges to achieve the aggressive performance goals required in advanced next-generation, leading-edge vision processors.

Inuitive excels at building multi-core processors that integrate the full range of intelligent vision technologies with superior performance, bandwidth, power and deep learning. Arteris IP interconnects enable us to meet our performance goals and facilitate the scalability of future products, helping us to accelerate our innovations."

Dor Zepeniuk, CTO and VP product, Inuitive

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Semiconductor Engineering article:

Optimizing NoC-Based Designs

May 5th, 2022 - By Paul Graykowski

Further optimization of RTL repartitioning with switching from crossbar interconnects to NoCs.

Semiconductor development is currently in a phase of rapid evolution driven by the combination of new technologies and methodologies. The technique of combining multiple functions into systems-on-chips (SoCs) is continuing to grow in complexity. Rapid advancement in new technologies for market segments like data centers, robotics, ADAS and artificial intelligence/machine learning (AI/ML) are resulting in a new breed of SoCs. These fields demand designs that are maximized for both power and performance efficiency. Designers are finding that networks-on-chip (NoCs) provide the enabling technology to meet this demand and are accelerating the move away from crossbar interconnect technology.

Learn more about Arteris IP Deployment Technology Products .

Configurability and Performance of FlexNoC is Key to Design of High-Performance Compute IP Platform for ADAS Applications

READING, UK and CAMPBELL, Calif. – May 3, 2022 -- Sondrel and Arteris IP (Nasdaq: AIP), a leading provider of system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate system-on-chip (SoC) creation, today announced that Sondrel is adopting FlexNoC interconnect IP in its next generation of advanced driver-assistance systems (ADAS) architecture. The onchip-interconnect was selected for its configurability and performance. The product enables the SFA 350A multi-channel automotive vehicle IP platform requirements. FlexNoC supports the ability to design the NoC to match the performance of IP blocks to ensure that data flows at the right speed in, out and around the SoC. It enables designers to quickly design and verify a chip that precisely meets the customer’s silicon specifications on time and within budget.

Through many years of working with Arteris, we knew that FlexNoc would reliably deliver exactly what we needed, backed up by excellent technical support. The SoC interconnect provides a complete, comprehensive solution spanning architecture exploration to physical implementation and verification."

Edwin Loverseed, Head of Engineering, Sondrel

 

CAMPBELL, Calif. – April 25, 2022 – Arteris IP (NASDAQ: AIP), a leading provider of system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate system-on-chip (SoC) creation, today announced that Functional Safety Manager Stefano Lorenzini will present at the Automotive IQ Application of ISO 26262 Conference on Wednesday, April 27, 2022, at Hilton Berlin, Germany. His keynote presentation, Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip, begins at 11:15 (CEST).

Veteran executive, Stanford lecturer and public company board member brings decades of relevant international corporate experience to Arteris IP

CAMPBELL, Calif. – April 5, 2022 – Arteris IP (NASDAQ: AIP), a leading provider of system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate system-on-chip (SoC) creation, today announced that Claudia Fan Munce will join Arteris IP’s Board of Directors and will commence her service at the company’s May 2022 board and committee meetings.

I’m very excited to welcome Claudia Fan Munce with her publicly traded company board stewardship and technology management experience to guide Arteris to the next stage in achieving our goals."

K. Charles Janac, President and CEO, Arteris IP

NoC interconnect IP to be dataflow backbone of German Federal Ministry of Education and Research (BMBF) project chip to advance automotive artificial intelligence and machine learning (AI/ML) processing.

CAMPBELL, Calif. – April 5, 2022 – Arteris IP (NASDAQ: AIP), a leading provider of system-on-chip (SoC) system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate SoC creation, today announced that BMW Group has licensed FlexNoC interconnect IP and the accompanying FlexNoC Resilience Package IP for use in a chip partially funded by the German Federal Ministry of Education and Research (BMBF) as part of the ZUSE-KI-mobil publicly funded project. The goal of the project is to develop an accelerator chip for high-end deep learning applications that is a leap forward in terms of energy efficiency, reliability, robustness and security, which go far beyond current possibilities. BMW Group is serving as the coordinator and leader of the project.

We are excited that the consortium led by BMW Group chose Arteris IP interconnect technology as the on-chip communications on-chip network for this innovative automotive system-on-chip. BMW Group’s decision to use our interconnect IP as the dataflow on-chip network of this complex system is a testimony to the benefits our technologies bring to design teams creating the world’s most sophisticated AI/ML processing chips."

K. Charles Janac, President and CEO, Arteris IP

This Electronic Design article, 'Making ISO 26262 Traceability Practical', covers Arteris IP's Harmony Trace in this piece authored by Paul Graykowski, Senior Technical Marketing Manager. 

March 4 , 2021 - By Paul Graykowski

The ISO 26262 standard states that functional-safety assessors should consider if requirements management, including bidirectional traceability, is adequately implemented. The standard doesn’t specify how an assessor should go about accomplishing this task. However, it’s reasonable to assume that a limited subset of connections between requirements and implementation probably doesn’t rise to the expectation.

For more information about Arteris Harmony Trace please visit: https://www.arteris.com/harmony-trace-design-data-intelligence

Guillaume Boillet, Senior Director of Product Management at Arteris IP authored this Semiconductor Engineering article:

Where Do Memory Maps Come From?

March 3rd, 2022 - By Guillaume Boillet

Ensuring software can accurately address hardware.

A memory map is the bridge between a system-on-chip (SoC) and the firmware and software that is executed on it. Engineers may assume the map automatically appears, but the reality is much more involved. The union of hardware (HW) and software (SW) demands both planning and compromise. The outcome of this merger will not be fully realized until the magical day when the system comes to life.

To learn more about SoC and Hardware/Software Interface (HSI) Development, please download this datasheet:  SoC & Hardware / Software Interface (HSI) Development Datasheet 

Bernard Murphy (SemiWiki) gets an update from Arteris IP.

An Ah-Ha Moment for Testbench Assembly 

February 28, 2022 - Bernard Murphy

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Design & Reuse article:

Traceability for Embedded Systems

February 3rd, 2022 - By Paul Graykowski

Maintaining connection between requirements and implementation is where traceability for embedded systems can show value. 

In an embedded system, the hardware/software interface (HSI) is a representation of requirements between hardware and software development teams. This description elaborates a huge wealth of detail in memory and IP register offsets, bitfields and detailed behavior specifications. In this representation, at least some aspects must be met precisely. This expectation is especially important because many designs must work with legacy software, not only to minimize development time but also to preserve reliability. A new device replacing one from a different vendor must often mirror all or most of the original HSI. In this context, capturing those requirements and using traceability to track compliance through development becomes a clear advantage.

To learn more about traceability and Arteris Harmony Trace, please download this technical paper: https://www.arteris.com/download-reinventing-traceability-arteris-harmony-trace-paper