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Arteris® IP FlexNoC® Interconnect & Resilience Package Again Licensed by Black Sesame for ISO 26262-Compliant Automotive ADAS Chips

Network-on-chip interconnect technology with integrated functional safety mechanisms accelerates development of automotive systems-on-chip. 

CAMPBELL, Calif. – June 8, 2021– Arteris IP, a leading provider of network-on-chip (NoC) interconnect and other intellectual property (IP) technology, that manages the on-chip communications in system-on-chip (SoC) semiconductor devices, today announced that Black Sesame Technologies has licensed Arteris FlexNoC interconnect IP and the accompanying FlexNoC Resilience Package for use in its ISO 26262-compliant automotive advanced driver assistance systems (ADAS) chips. 

We successfully used the Arteris FlexNoC interconnect IP and Resilience Package in our previous generation ISO 26262 ASIL B systems and have been impressed with Arteris IP's product maturity, performance and functional safety capabilities. The Arteris IP FlexNoC interconnect and Resilience Package truly helped us more quickly develop our complex ADAS SoCs, which incorporate extensive artificial intelligence hardware acceleration, while providing the required functional safety mechanisms for us to achieve ISO 26262 compliance. In addition, the local Arteris IP engineering support team provided valuable architectural and functional safety feedback as we developed our chips.”


David Zeng, Senior VP, Black Sesame

Topics: automotive semiconductors Arteris FlexNoC flexnoc resilience package ADAS ISO 26262 compliance artificial intelligence ADAS SoC

Semiconductor Engineering: Big Changes Ahead For Connected Vehicles

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

Big Changes Ahead For Connected Vehicles

June 3rd, 2021 - By Ann Steffora Mutschler

Tapping into multiple services, both inside and outside a car, requires a rethinking of everything from architectures to security.

“When you look at the geography of the car, you have to consider how to chop things up,” said Kurt Shuler, vice president of marketing at Arteris IP. “As part of the ECU consolidation discussion, zonal can be one approach such that, for example, ‘the antilock braking system is usually next to this other subsystem, so let’s put those together, and we’ll make that one electronic system that’ll cover all that stuff.’ However, there are still some who say all of this is going to go together, like a centralized architecture where there is a common brain, which makes sense from a functional safety and redundancy standpoint.”

Topics: SoC NoC network-on-chip automotive semiconductor engineering arteris ip interconnects Tier-1 automotive supplier automotive OEMs ECUs service-oriented architectures SOAs zonal architectures Tier 2

Semiconductor Engineering: Automotive AI Hardware: A New Breed

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article in Semiconductor Engineering:

Automotive AI Hardware: A New Breed

June 3rd, 2021 - By Kurt Shuler

What sets automotive apart from the conventional wisdom on AI hardware markets.

Arteris IP functional safety manager Stefano Lorenzini recently presented “Automotive Systems-on-Chip (SoCs) with AI/ML and Functional Safety” at the Linley Processor Conference. A main point of the presentation was that conventional wisdom on AI hardware markets is binary. There’s AI in the cloud: Big, power-hungry, general-purpose. And there’s AI at the edge: Small, low power, limited application-specific features. Automotive AI doesn’t really fit into either category. To power ADAS and autonomous driving functions, these chips are extremely application-specific and require more performance than typical edge AI, are low power but not as low as IoT chips at the edge, and must be as low cost as possible. They also add a new angle – low latency because safety demands fast and deterministic response times. Add to all that the functional safety requirements demanded by ISO 26262 – inside the AI structure as much as everywhere else. Bottom line: Automotive AI SoC architectures are unique beasts.

Topics: SoC NoC functional safety network-on-chip automotive ECC The Linley Group ISO 26262 compliance semiconductor engineering arteris ip interconnects kurt shuler AI SoCs AI/ML Stefano Lorenzini heterogeneous socs ASIL

SemiWiki: IP-XACT Resurgence, Design Enterprise Catching Up

Isabelle Geday, VP & GM of the new IP Deployment Division at Arteris IP, gives Bernard Murphy (SemiWiki) insight into some motivations driving companies to switch to IP-XACT.

IP-XACT Resurgence, Design Enterprise Catching Up

June 3, 2021 - Bernard Murphy

This standard has been around in one form or another for over ten years and was then arguably ahead of its time. RTL designers were confused: ‘We already have RTL. Why do we need something else?’ I also didn’t get it. Still, the standard plugged ahead among the faithful and found traction among IP vendors. Particularly as a common format to distribute non-RTL data, like register maps. But a lot has been changing in the meantime. Faster moving competitors. More horizontal and vertical dependencies. Mergers and acquisitions. Chinese technology growth and competition. To adapt, some top-tier organizations have already fully embraced IP-XACT, others are now racing to catch up. Why? Rather than making a dry technical case, I’ll share a few real examples (no names).
Topics: SoC NoC network-on-chip semiconductor arteris ip semiwiki ip-xact RTL noc interconnect AI SoCs Isabelle Geday AI/ML IPD

SemiWiki: Architecture Wrinkles in Automotive AI: Unique Needs

Bernard Murphy (SemiWiki) learns from Stefano Lorenzini, Functional Safety Manager at Arteris IP, the difference between AI in automotive and other contexts. 

Architecture Wrinkles in Automotive AI: Unique Needs

May 20th, 2021 - Bernard Murphy

Arteris IP recently spoke at the Spring Linley Processor Conference on April 21, 2021 about Automotive systems-on-chips (SoCs) architecture with artificial intelligence (AI)/machine learning (ML) and Functional Safety. Stefano Lorenzini, Functional Safety Manager at Arteris IP, presented a nice contrast between auto AI SoCs and those designed for datacenters. Never mind the cost or power, in a car we need to provide near real-time performance for sensing, recognition and actuation. For IoT applications we assume AI on a serious budget, power-sipping, running for 10 years on a coin cell battery. But that isn't the whole story. AI in the car is a sort of hybrid, with the added dimension of safety, which makes for unique architecture wrinkles in automotive AI.  
Topics: SoC NoC network-on-chip semiconductor ECC The Linley Group FlexNoC arteris ip semiwiki functional safety manager kurt shuler data centers noc interconnect AI SoCs AI/ML automotive AI Hardware Stefano Lorenzini

Semiconductor Engineering: Power Optimization: What's Next?

Guillaume Boillet, Director of Product Management at Arteris IP is quoted in this new article in Semiconductor Engineering:

Power Optimization: What's Next!

May 17th, 2021 - By Brian Bailey

Clock gating and power gating were a good start, but there is much more that can and should be done to minimize power.

“The efforts in terms of methodology, compute resources and engineering talent to deploy system-level techniques are definitely non-negligible,” says Guillaume Boillet, director of product management for Arteris IP. “Only the most advanced and power-savvy design teams invest in those.”

Topics: SoC NoC network-on-chip dynamic power machine learning semiconductor engineering arteris ip interconnects RTL Guillaume Boillet clock-gating macro-level

Arteris IP Welcomes Back Veteran Laurent Moll as Chief Operating Officer

As a top industry executive, holding prior roles at Qualcomm and NVIDIA, Moll Brings strategic leadership as the company drives system-on-chip IP integration growth.

CAMPBELL, Calif. – April 14, 2021 – Arteris IP, a leading provider of network-on-chip (NoC) interconnect and other intellectual property (IP) technology that manages the on-chip communications in system-on-chip (SoC) semiconductor devices, today announced it is proud to welcome Laurent Moll as Chief Operating Officer (COO). Laurent will be responsible for managing all aspects of engineering functions and operations at Arteris IP. He will participate in the company’s growth strategies and oversee the successful delivery of its industry-leading semiconductor designs as Arteris IP increases in scope and market share.

We are excited to welcome Laurent back to our team at Arteris IP. Laurent will not only bring his expertise and experience to focus on our company's technology evolution but will also provide additional leadership to solidify our SoC integration IP position.”


K. Charles Janac, President and CEOArteris IP

Topics: SoC NoC laurent moll on-chip interconnect automotive nvidia K. Charles Janac IP market COO qualcomm system-on-chip development

Arteris® IP Adds a Record 28 New Licensees in 2020

Network-on-Chip (NoC) semiconductor IP growth driven by customer development of new automotive, machine learning, 5G & data center system-on-chip (SoCs).

CAMPBELL, Calif. – February 17, 2021 – Arteris IP, a leading provider of network-on-chip (NoC) interconnect and other intellectual property (IP) technology that manages the on-chip communications in system-on-chip (SoC) semiconductor devices, today announced that the company added 28 new licensees for its Arteris® IP Ncore®, FlexNoC®, CodaCache®, AI Package, Resilience Package, and PIANO® Interconnect IP products in 2020. With the addition of these 28 new licensees, the cumulative number of Arteris IP semiconductor IP licensees throughout the company’s history reached 159. SoC design starts throughout the company’s history exceeded 500 chip projects. Furthermore, two large semiconductor vendor customers signed multi-year licensing deals with the company.

Despite the COVID headwinds, Arteris IP had a strong year based on both technology delivery and customer acquisition gains. Our focus on automotive, machine learning, 5G and data center applications has provided increased competitive value to our customers, who rewarded Arteris IP with an unprecedented number of SoC design wins.”


K. Charles Janac, President and CEOArteris IP

Topics: SoC NoC on-chip interconnect automotive AI K. Charles Janac ip-xact ML 5G IP market Isabelle Geday IP Deployment Division Board of Directors IPDD data center systems-on-chip GUI Tcl

Arteris® IP Adds Two Veteran Executives to its Board of Directors

Network-on-Chip (NoC) semiconductor IP leader adds Raman Chitkara and Isabelle Geday to its Board of Directors 

CAMPBELL, Calif. – February 10, 2021 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Raman Chitkara and Isabelle Geday have joined its Board of Directors.

I am excited to be working with board members of Raman's and Isabelle's caliber and talent. With Raman's knowledge of accounting best practices and Isabelle's strong European and software management experience, we have a skilled and knowledgeable team of board members who will help navigate the evolution of Arteris IP.”


K. Charles Janac, President and CEOArteris IP

Topics: SoC NoC on-chip interconnect AI K. Charles Janac ML IP market Isabelle Geday IP Deployment Division Raman Chitkara Board of Directors

Arteris® IP FlexNoC® Interconnect and Resilience Package Supports Socionext's 5nm Automotive Chip Production

Automotive chip design leader standardizes on Network-on-Chip (NoC) interconnect IP for multiple ISO 26262-compliant systems-on-chip (SoCs)

CAMPBELL, Calif. and YOKOHAMA, Japan– February 4, 2021 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Socionext has implemented Arteris® FlexNoC® interconnect IP and the accompanying Resilience Package in multiple automotive chips, including an automotive SoC fabricated using 5nm semiconductor process technology.

We are able to more efficiently design large scale automotive chips because we are able to see early in the design process the layout impacts of our SoC and NoC architecture choices. This is especially important when using leading edge 5nm semiconductor process technologies. Furthermore, our SoC functional safety architecture has been enhanced by the novel technologies in the FlexNoC interconnect IP Resilience Package, allowing us to quickly tailor safety mechanisms for the desired ISO 26262 ASIL to meet our customers’ demanding schedules."


Kaichi Yamashita, Head of the Automotive Business Unit, Socionext

Topics: SoC NoC functional safety network-on-chip on-chip interconnect flexnoc resilience package ADAS iso 26262 ASIL K. Charles Janac customer automotive chips IP market Socionext 5nm