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Apr 16, 2026

Design & Reuse: Topology and Data Movement in Multi-Die Design

This article explores how multi-die design shifts the primary challenge from scaling silicon to managing data movement and system integration across chiplets. It highlights the critical role of NoC topology in controlling traffic, latency, and coherency between dies, as well

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Apr 1, 2026

The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)

Modern system-on-chip (SoC) performance is no longer compute-bound. It is increasingly data-movement–bound and wire-limited.

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Mar 30, 2026

Arteris × XuanTie: The “Data Highway” for High-Performance RISC-V SoCs

Arteris and XuanTie have formed a deep partnership, leveraging the Ncore cache-coherent NoC IP as the core to build a "data highway" for high-performance RISC-V SoCs. Ncore paired with the XuanTie C930 delivers 30 GB/s/GHz bandwidth and 110-cycle latency, supporting

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Mar 26, 2026

Building Secure Chips: Why Hardware Security Assurance Is Now Essential

Hardware security is no longer optional. At DAC 2025, industry leaders share how teams are shifting from traditional verification to measurable security assurance without breaking budgets or schedules. Learn what’s changing, why it matters, and how to build trust into

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Mar 26, 2026

Semiconductor Engineering: Importance Of Hardware Security Verification In Pre-Silicon Design

Security in modern semiconductor design must be built in from the start, not validated after the fact. This article explains how pre-silicon hardware security verification relies on two key pillars — functional verification to ensure security features behave correctly, and

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Mar 18, 2026

EDN: Chiplet innovation isn’t waiting for perfect standards

As monolithic SoCs reach their limits, chiplets offer a more scalable and cost-effective path forward. Despite incomplete standards, companies are moving ahead using modular design and flexible interconnects, with Arteris highlighting the role of NoC IP and automation in enabling

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Mar 6, 2026

EDN: Last-level cache has become a critical SoC design element

As AI-driven SoCs integrate increasingly heterogeneous compute engines, last-level cache (LLC) has become a critical architectural element for balancing performance, power, and determinism. Positioned between on-chip subsystems and external memory, LLC reduces latency and off-chip traffic but only when carefully

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Mar 2, 2026

SemiWiki: Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain

As RISC-V adoption grows across commercial and government programs, integrating third-party IP cores introduces supply chain security challenges that require structured, design-level assurance. This article highlights a scalable, CWE-based methodology demonstrated by Cycuity (an Arteris brand) with SiFive and BAE

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Feb 26, 2026

Semiconductor Engineering: AI Energy Gap and Chiplets: Why Data Movement Matters

At the panel discussion at Chiplet Summit 2026, where Arteris was among the experts, participants emphasized that efficient AI chiplets require more than fast physical links like UCIe—they demand smart, system-level architecture around data movement, coherency, and protocol choice. As

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Feb 24, 2026

Electronic Design: Bridging the Gap to Chiplet Interoperability

This article examines the gap between today’s tightly managed multi-die implementations and the long-term vision of true multi-vendor chiplet interoperability. It explains how companies are deploying homogeneous and heterogeneous architectures, why proprietary flows still limit plug-and-play integration, and how standards

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