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From Bug Hunting to Engineering Methodology

From Bug Hunting to Engineering Methodology: Lessons from AI-Driven Development 

This article explains how AI can speed up engineering research and bug discovery when engineers can verify the results. Drawing on the work developing Arteris’ JIG C++ verification library, it shows how built-in checks give AI clear criteria to explore

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Data Center AI at the Power Limit: When Data Movement Defines Performance

HPCwire: Data Center AI at the Power Limit: When Data Movement Defines Performance

This article explains how power limits are reshaping data center AI design, making efficient, predictable data movement across heterogeneous compute, memory and chiplet architectures central to system performance. He highlights the role of intelligent interconnect and automation in keeping compute

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A Network-on-Chip (NoC) For Multi-Die Devices

Semiconductor Engineering: A Network-on-Chip (NoC) For Multi-Die Devices

This article explains how extending native NoC packet traffic across die boundaries can support efficient, scalable data movement for multi-die systems, especially physical AI and automotive platforms.

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SoC and NoC in the Chiplet Era: Understanding Modern SoC Architecture

Learn how SoCs and NoCs work together in modern semiconductor design and why chiplet-based architectures make intelligent data movement more critical than ever.

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The Cyber Resilience Act Is Turning Hardware Security into an Evidence Question

The Cyber Resilience Act Is Turning Hardware Security into an Evidence Question

A passing security test has two explanations. As the EU Cyber Resilience Act takes effect, security coverage shows what hardware verification actually reached

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Beyond the Die Boundary How Arteris Multi-Die Technology Is Redefining AI System Design

Beyond the Die Boundary: How Arteris Multi-Die Technology Is Redefining AI System Design 

See why the Arteris Multi-Die Solution earned a Stevie Award for helping design teams turn complex chiplet architectures into unified systems with scalable data movement, streamlined integration, and a predictable path to silicon.

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AI-Driven Development: Why Verification Matters More Than Ever

AI-Driven Development: Why Verification Matters More Than Ever 

Discover why AI works best as an engineering partner, helping development teams explore solutions faster, while verification ensures reliable results.

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How Cache Coherency Simplifies AI Software

Semiconductor Engineering: How Cache Coherency Simplifies AI Software

This article explains how hardware-managed cache coherency can simplify AI software by coordinating shared data across CPUs, accelerators and chiplets. The article highlights the role of coherent and non-coherent interconnects in building scalable, efficient AI SoCs, while presenting Arteris’ Ncore,

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Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects

Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects

Learn how ISO 26262 Part 11 helps semiconductor architects build safer automotive SoCs through architectural planning, automation, and functional safety.

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EDN Hardware security verification must go beyond functional testing

EDN: Hardware security verification must go beyond functional testing

This article explains why functional testing alone cannot uncover the unintended data paths and hardware–firmware interactions that create security risks, and how Cycuity Radix enables teams to define verifiable security requirements, detect violations and measure security coverage across simulation and

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