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Magillem Registers provides a single source of truth
Semiconductor Engineering: CSR Management: Life Beyond Spreadsheets
The hardware-software interface (HSI) that’s physically represented by control and status registers (CSRs) is a critical source of design risk. Mismanagement of CSRs contributes to a number of SoC failures. To avoid these setbacks, engineering teams need a robust, automated
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EDN: Boosting RISC-V SoC performance for AI and ML applications
Modern SoC designs are more innovative and complex than ever, therefore RISC-V-based designs must address challenges like interoperability, hardware-software integration, and safety certifications to meet stringent performance and reliability standards. Learn more in this article.
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Electronic Design: Breaking Barriers in SoC Design with Smart NoC Automation
As SoCs grow in complexity, manual NoC generation is no longer practical. Discover how how automated NoC generation streamlines interconnect development to improve efficiency, scalability, and performance in advanced semiconductor designs.
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Semiconductor Engineering: Data Movement Is the Energy Bottleneck of Today’s SoCs
In today’s AI-focused semiconductor landscape, raw compute performance alone no longer defines the effectiveness of a system-on-chip (SoC). Learn more about how the right interconnect ensures that design teams are well-equipped to meet workload demands while achieving the performance and
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Unite.AI: Andy Nightingale, VP of Product Marketing at Arteris – Interview Series
Learn more about Andy Nightingale, VP of Product Marketing at Arteris. Throughout his 35-year career, Andy has held a range of roles, including engineering and product management positions at Arm, where he spent 23 years. In his current role, Andy
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Magillem Registers: Hardware Software Interface Foundation For Design Innovation
Design & Reuse: Automating Hardware-Software Consistency in Complex SoCs
Magillem Registers automates hardware-software consistency, ensuring consistency, reducing errors, and accelerating development for efficient, innovative, and reliable designs.
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EDN: How NoC architecture solves MCU design challenges
Explore how today's NoC architectures solve MCU design challenges by optimizing timing closure, minimizing wire count, and reducing die area while supporting high-bandwidth, low-latency communication.
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Design News: The Hidden Technology Behind Faster, Smarter Silicon Chips
Engineering time can be significantly reduced thanks to the use of smart NoC IP technology like FlexGen smart NoC IP from Arteris. Learn more in the article.
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Semiconductor Engineering: Challenges In Managing Chiplet Resources
The chip industry is exploring multiple avenues for simplifying multi-die integration, but difficulties remain for optimizing designs. Learn more in the article.
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Semiconductor Engineering: Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
As design complexity increases, manual design approaches can struggle to minimize wire length. Learn more about how the solutions like Arteris’ FlexGen can help one optimize that.
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