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Data movement is the new performance battleground in semiconductor design
TechRadar: Data movement is the new performance battleground in semiconductor design
The article highlights why interconnect design must become a first-class architectural consideration, with quality of service, determinism and physically aware automation playing key roles across AI data centers, physical AI and multi-die systems.
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The Missing Layer in AI Systems Design is Predictable, Scalable Data Movement
Electronic Design: The Missing Layer in AI Systems Design is Predictable, Scalable Data Movement
The article explores why predictable, scalable data movement is becoming a critical architectural requirement for AI systems as compute complexity and bandwidth demands continue to grow.
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Last-Level Caches Matter Even More in the HBM Era
Embedded: Last-Level Caches Matter Even More in the HBM Era
The article explains why last-level caches (LLCs) are becoming even more important as high-bandwidth memory (HBM) is adopted for AI and high-performance computing.
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Advancing Europe’s Automotive Innovation Ecosystem: Arteris Continues Its Work in the RIGOLETTO Project
Advancing Europe’s Automotive Innovation Ecosystem: Arteris Continues Its Work in the RIGOLETTO Project 
As software-defined vehicles reshape the automotive industry, collaborative innovation is becoming essential to developing secure, scalable computing platforms. Learn how Arteris is contributing to the European RIGOLETTO project, helping advance next-generation automotive architectures through expertise in Network-on-Chip technology, RISC-V integration,
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Avoid The Hidden Bottleneck Of Integration At Scale
Semiconductor Engineering: Avoid The Hidden Bottleneck Of Integration At Scale
This Semiconductor Engineering article examines how SoC integration has become a major bottleneck as designs scale in complexity, with growing numbers of IP blocks, registers, and hardware/software interfaces.
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Making chiplets work for AI requires more than connectivity
The AI Journal: Making chiplets work for AI requires more than connectivity
This article explains why building successful AI chiplet architectures requires more than high-speed die-to-die connectivity. It explores how efficient data movement, protocol selection, coherency, and intelligent NoC architecture are critical to maximizing performance, scalability, and energy efficiency in next-generation AI
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What the Cyber Resilience Act means for the future of chip design
What the Cyber Resilience Act means for the future of chip design
The EU Cyber Resilience Act is reshaping semiconductor security, making cybersecurity, compliance, and lifecycle management core design priorities.
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Reducing Avoidable Memory Trips In HBM Systems
Semiconductor Engineering: Reducing Avoidable Memory Trips In HBM Systems
As AI and high-performance SoCs increasingly rely on HBM, memory bandwidth alone is no longer enough to maximize performance. This article discusses why the intelligent data movement and cache efficiency are critical to unlocking the full benefits of HBM-based architectures.
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Heterogeneous Computing and AI SoCs
Beyond Moore’s Law: Heterogeneous Computing and AI SoCs
As Moore’s Law slows, heterogeneous computing is driving AI, automotive, and data center innovation through specialized compute, chiplets, and advanced interconnects.
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Model your IPs and your NoCs
EDN: Model your IPs and your NoCs
As SoC and chiplet architectures become increasingly complex, effective modeling must extend beyond functional IP blocks to include the NoC interconnect fabric itself. This article highlights why NoCs have become critical determinants of system performance and explains the value of
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