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How Network-on-Chip architectures are powering the future of microcontroller design
Power Electronics Magazine: How Network-on-Chip Architectures Are Powering the Future of Microcontroller Design 
Network-on-Chip (NoC) technology is redefining how microcontrollers (MCUs) handle performance, power efficiency, and scalability. As MCUs take on more complex, AI-driven, and safety-critical tasks, NoC architectures provide the structured, high-speed interconnects needed to keep pace. Learn more about how Arteris
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Efficiency Defines Future of Data Movement
Semiconductor Engineering: Efficiency Defines The Future Of Data Movement
As AI workloads expand and chiplet architectures evolve, data movement now consumes more energy than computation itself. Achieving higher performance within fixed power budgets demands efficient, intelligent interconnects and automation across multi-die SoC designs. Learn more in the article.
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A Guide to Building Chiplets Today While Shaping Tomorrow’s Standards
EE Times: A Guide to Building Chiplets Today While Shaping Tomorrow’s Standards
Chiplet standards like UCIe, AIB, and BoW are still evolving, but design teams can start building with chiplets today by adopting packaging automation, structured IP metadata, and scalable interconnect fabrics that enable flexibility and future-proof integration. Learn how to design
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A Logically Correct SoC Design Isn’t an Optimized Design
EDN: A Logically Correct SoC Design Isn’t an Optimized Design
Automation in SoC design is evolving beyond correctness toward true optimization. Just as modern GPS systems account for real-world traffic, AI-driven, physically aware automation for NoC design minimizes wire length, manages congestion, and adapts dynamically to design changes — closing
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Semiconductor Engineering: The Future Of SoC Design Is Data Movement
The semiconductor industry is shifting from focusing on raw compute to tackling the growing challenge of data movement in complex SoCs. With advances in chiplets, high-bandwidth memory, CXL fabrics, and automotive zonal architectures, predictable performance now depends on layered, automated,
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Electronic Design: Speeding the Process of Building IPs, Chiplets, and SoCs
Designing modern SoCs and multi-die systems requires faster integration of thousands of IP blocks and chiplets while minimizing errors. Structured metadata standards like IP-XACT, combined with automation, are transforming this process by ensuring consistency, tool interoperability, and accurate hardware/software alignment
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Critical Safety Overview and Definitions
Critical Safety Overview and Definitions
Overview of critical safety systems and functional safety standards in automotive, focusing on ISO 26262 compliance and its impact on SoC design and performance.
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NoC Interconnect Fabric IP Improves SoC Power, Performance and Area
NoC Interconnect IP Improves SoC Power, Performance and Area
Explore how Arteris' NoC interconnect IP enhances SoC power efficiency, performance, and area, driving advancements in complex semiconductor designs.
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High-level representations of common NoC Topologies
SoC Interconnect Fabric: A Brief History from Buses to the NoCs of Today and Tomorrow
Explore the evolution of SoC interconnect fabrics from buses to advanced NoCs, highlighting their impact on modern high-performance computing and efficient system integration.
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Efficient IP Packaging for Today’s SoC Integration
Design & Reuse: Efficient IP Packaging for Today’s SoC Integration
As SoC architectures scale in complexity, managing hundreds of IP blocks consistently from concept through production is critical to avoid costly errors and rework. Standardizing IP descriptions with IEEE 1685 (IP-XACT) and automating packaging ensures interoperability, accelerates design, and promotes
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