Contact Us
Generic selectors
Exact matches only
Search in title
Search in content
Post Type Selectors

Blogs

background-element-24

Sort & Filter

Topics
Tags filter
Show More
Year filter
Show More
Latest
Oldest
A-Z
Z-A
394 Results
Sort & Filter
The Data Dilemma: Cracking the Code of Data Movement for the Next Wave of Semiconductor Innovation
EE Times: The Data Dilemma: Cracking the Code of Data Movement for the Next Wave of Semiconductor Innovation
As semiconductor architectures scale toward chiplets, multi-die SoCs, and AI-driven workloads, data movement—not raw compute—has emerged as the primary limiter of performance, power, and scalability. The article argues that network-on-chip fabrics are becoming the true center of gravity in modern
Learn more about post
SoC performance is dependent upon data availability
Semiconductor Engineering: Solving Real-World AI Bottlenecks
This article explains how modern AI SoCs are increasingly limited by data movement and memory latency rather than raw compute. It highlights the role of efficient interconnects and shared last-level caches in reducing latency, power consumption, and DRAM traffic, and
Learn more about post
AI workloads demand smarter SoC interconnect design - EDN
EDN: AI workloads demand smarter SoC interconnect design
This EDN article explains how AI workloads are pushing traditional SoC interconnect design beyond practical limits, making intelligent automation essential. Physically aware NoC algorithms optimize topology, power, latency, and timing closure, enabling scalable AI SoCs from data centers to the
Learn more about post
2026 Predictions: System-Level Design, AI-Native Workflows, and the Rise of Multi-Die Compute Fabrics
2026 Predictions: System-Level Design, AI-Native Workflows, and the Rise of Multi-Die Compute Fabrics 
Explore 2026 semiconductor predictions as AI accelerates system-level design, multi-die compute fabrics, chiplets, 2.5D/3D integration, and AI-native architecture workflows reshape how advanced systems are built and verified.
Learn more about post
Advancing Europe’s Automotive Chiplet Vision: Arteris Joins CHASSIS to Accelerate Software-Defined Mobility
Advancing Europe’s Automotive Chiplet Vision: Arteris Joins CHASSIS to Accelerate Software-Defined Mobility
Arteris joins CHASSIS, Europe’s open automotive chiplet initiative with advanced NoC and multi-die interconnect technology that accelerates software-defined mobility.
Learn more about post
A Golden Source As The Single Source Of Truth In HSI
Semiconductor Engineering: A Golden Source As The Single Source Of Truth In HSI
Maintaining alignment between hardware and software is one of the biggest challenges in complex SoC design. A single, machine-readable golden source keeps every element from RTL to drivers and documentation perfectly synchronized. Learn how Arteris’ Magillem Platform makes this possible
Learn more about post
How Network-on-Chip architectures are powering the future of microcontroller design
Power Electronics Magazine: How Network-on-Chip Architectures Are Powering the Future of Microcontroller Design 
Network-on-Chip (NoC) technology is redefining how microcontrollers (MCUs) handle performance, power efficiency, and scalability. As MCUs take on more complex, AI-driven, and safety-critical tasks, NoC architectures provide the structured, high-speed interconnects needed to keep pace. Learn more about how Arteris
Learn more about post
Efficiency Defines Future of Data Movement
Semiconductor Engineering: Efficiency Defines The Future Of Data Movement
As AI workloads expand and chiplet architectures evolve, data movement now consumes more energy than computation itself. Achieving higher performance within fixed power budgets demands efficient, intelligent interconnects and automation across multi-die SoC designs. Learn more in the article.
Learn more about post
A Guide to Building Chiplets Today While Shaping Tomorrow’s Standards
EE Times: A Guide to Building Chiplets Today While Shaping Tomorrow’s Standards
Chiplet standards like UCIe, AIB, and BoW are still evolving, but design teams can start building with chiplets today by adopting packaging automation, structured IP metadata, and scalable interconnect fabrics that enable flexibility and future-proof integration. Learn how to design
Learn more about post
A Logically Correct SoC Design Isn’t an Optimized Design
EDN: A Logically Correct SoC Design Isn’t an Optimized Design
Automation in SoC design is evolving beyond correctness toward true optimization. Just as modern GPS systems account for real-world traffic, AI-driven, physically aware automation for NoC design minimizes wire length, manages congestion, and adapts dynamically to design changes — closing
Learn more about post

No results found

Make sure all words are spelled correctly. Try different, more general, or fewer keywords.

Call to Action
Media Resources

Media Contact

Gina Jacobs

VP Brand Marketing
+1 408 560 3044
Contact Newsroom

Media Resources

Logo Guidelines
Logo Download
Company Overview