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‘Hardening’ SoCs For Automotive Market Challenges
Migrating SoC designs from mobility into new markets like automotive creates new issues for reliability, security and quality of service.
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What Does It Cost You When Your SoC is Late to Market?
SoC Design Cost Chip Late Market Interconnect
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The Critical Cost of Routing Congestion
The growing expense of wire routing congestion in your SoC design may be costing you critical design wins.
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Arteris Emerges Strong in 2014 As Semiconductor Markets Diversify
National Hockey League Hall of Famer Wayne Gretzky famously once said, “A good hockey player plays where the puck is. A great hockey player plays where the puck is going to be.”
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SemiEngineering: The Uncertain Future Of Fabless Semis
System OEMs are driving more and more SoC requirements, and even designing SoCs themselves.
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Divide & Conquer: Dispersed global design teams need NoC fabric IP
Dispersed global design teams can “divide & conquer” SoC design and verification if they use NoC interconnect fabric IP. SoC reassembly is the key.
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System-Level Design Arteris CTO interview: Faster IP Integration
System-Level Design sat down with Laurent Moll, chief technology officer at Arteris to talk about interoperability, complexity & integration issues.
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The Semiconductor Industry Needs an IP Switzerland
It’s official: The great IP land grab has begun. The process actually has been taking place gradually, but has accelerated with Imagination Technologies’ acquisition of MIPS last year and, most recently, Cadence’s acquisition of Tensilica. For makers of semiconductors, four
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Advanced SoC Interconnect IP Enables Greater Flexibility in an Era of Consolidation
I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year. But before we let go of 2012, it’s important to reflect on the past year and see what
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